diff --git a/insns/insn_SB_type.py b/insns/insn_SB_type.py
index d202fed..e92ef6a 100644
--- a/insns/insn_SB_type.py
+++ b/insns/insn_SB_type.py
@@ -27,12 +27,4 @@ class rvfi_insn_SB_type(rvfi_insn_general):
         m.d.comb += self.misa_ok.eq(1)
         m.d.comb += self.ialign16.eq(0)
 
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m
diff --git a/insns/insn_beq.py b/insns/insn_beq.py
index 6bb4708..48aa0c6 100644
--- a/insns/insn_beq.py
+++ b/insns/insn_beq.py
@@ -18,5 +18,13 @@ class rvfi_insn_beq(rvfi_insn_SB_type):
         m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
+        
+        # default assignments
+        m.d.comb += self.spec_rd_addr.eq(0)
+        m.d.comb += self.spec_rd_wdata.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m