M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Update README.md

This commit is contained in:
Donald Sebastian Leung 2020-08-26 17:21:27 +08:00
parent 46e6ca3f70
commit 3f3ec597a1
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
rvfi/insns/README.md
View File

@ -84,6 +84,15 @@ Below is a list of instructions currently supported by this port of the riscv-fo
- `InsnRV32IUType`: RV32I U-Type Instruction
- `InsnLui`: LUI instruction
- `InsnAuipc`: AUIPC instruction
- `InsnRV32MRType`: RV32M R-Type Instruction
- `InsnMul`: MUL instruction
- `InsnMulh`: MULH instruction
- `InsnMulhsu`: MULHSU instruction
- `InsnMulhu`: MULHU instruction
- `InsnDiv`: DIV instruction
- `InsnDivu`: DIVU instruction
- `InsnRem`: REM instruction
- `InsnRemu`: REMU instruction
### ISAs
@ -100,3 +109,4 @@ The following core-specific parameters are currently supported:
| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
| `params.compressed` | Support for compressed instructions | `True`, `False` |
| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
| `params.altops` | Use alternative operations for multiplication/division | `True`, `False` |