From 3f3ec597a1bece1860e20af8959f1ef803a02472 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Wed, 26 Aug 2020 17:21:27 +0800
Subject: [PATCH] Update README.md
---
rvfi/insns/README.md | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/rvfi/insns/README.md b/rvfi/insns/README.md
index 13960ff..61fde50 100644
--- a/rvfi/insns/README.md
+++ b/rvfi/insns/README.md
@@ -84,6 +84,15 @@ Below is a list of instructions currently supported by this port of the riscv-fo
- `InsnRV32IUType`: RV32I U-Type Instruction
- `InsnLui`: LUI instruction
- `InsnAuipc`: AUIPC instruction
+ - `InsnRV32MRType`: RV32M R-Type Instruction
+ - `InsnMul`: MUL instruction
+ - `InsnMulh`: MULH instruction
+ - `InsnMulhsu`: MULHSU instruction
+ - `InsnMulhu`: MULHU instruction
+ - `InsnDiv`: DIV instruction
+ - `InsnDivu`: DIVU instruction
+ - `InsnRem`: REM instruction
+ - `InsnRemu`: REMU instruction
### ISAs
@@ -100,3 +109,4 @@ The following core-specific parameters are currently supported:
| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
| `params.compressed` | Support for compressed instructions | `True`, `False` |
| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
+| `params.altops` | Use alternative operations for multiplication/division | `True`, `False` |