From 060dd9891979670857f180c7ff967adbaf416373 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 14:00:12 +0800 Subject: [PATCH] Add SUB instruction --- insns/InsnSub.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSub.py diff --git a/insns/InsnSub.py b/insns/InsnSub.py new file mode 100644 index 0000000..85bf28c --- /dev/null +++ b/insns/InsnSub.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSub(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) + def elaborate(self, platform): + m = super(InsnSub, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata - self.rvfi_rs2_rdata, 0)) + + return m