2020-08-07 15:33:18 +08:00
|
|
|
from InsnRV32IRType import *
|
|
|
|
|
|
2020-08-07 16:06:15 +08:00
|
|
|
"""
|
|
|
|
|
SLTU instruction
|
|
|
|
|
"""
|
|
|
|
|
|
2020-08-07 15:33:18 +08:00
|
|
|
class InsnSltu(InsnRV32IRType):
|
|
|
|
|
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
2020-08-10 11:15:05 +08:00
|
|
|
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011)
|
2020-08-07 15:33:18 +08:00
|
|
|
def elaborate(self, platform):
|
2020-08-10 11:15:05 +08:00
|
|
|
m = super().elaborate(platform)
|
2020-08-07 15:33:18 +08:00
|
|
|
|
|
|
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, 0))
|
|
|
|
|
|
|
|
|
|
return m
|
