riscv-formal-nmigen/README.md

# riscv-formal-nmigen

A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

## Dependencies

- [nMigen](https://github.com/m-labs/nmigen)

## Build

TODO

## Support

The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.

## License

See [LICENSE](./LICENSE)
Initial commit 2020-07-14 10:30:37 +08:00			`# riscv-formal-nmigen`

Copy license from source 2020-07-14 10:42:06 +08:00			`A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen`
Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00
			`## Dependencies`

			`- [nMigen](https://github.com/m-labs/nmigen)`

			`## Build`

			`TODO`

Mention expected scope of project in README 2020-07-21 17:55:28 +08:00			`## Support`

Update README.md 2020-07-22 16:44:46 +08:00			`The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.`
Mention expected scope of project in README 2020-07-21 17:55:28 +08:00
Add LUI instruction for RV32I 2020-07-21 16:13:52 +08:00			`## License`

			`See [LICENSE](./LICENSE)`