29 lines
1.2 KiB
Python
29 lines
1.2 KiB
Python
|
from Insn import *
|
||
|
|
|
||
|
|
"""
|
||
|
|
RV32I R-Type Instruction
|
||
|
|
"""
|
||
|
|
|
||
|
|
class InsnRV32IRType(Insn):
|
||
|
|
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct7, funct3, opcode):
|
||
|
|
super(InsnRV32IRType, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
|
||
|
|
self.funct7 = funct7
|
||
|
|
self.funct3 = funct3
|
||
|
|
self.opcode = opcode
|
||
|
|
def elaborate(self, platform):
|
||
|
|
m = super(InsnRV32IRType, self).elaborate(platform)
|
||
|
|
|
||
|
|
if self.RISCV_FORMAL_CSR_MISA:
|
||
|
|
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||
|
|
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||
|
|
else:
|
||
|
|
m.d.comb += self.misa_ok.eq(1)
|
||
|
|
|
||
|
|
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == self.funct7) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == self.opcode))
|
||
|
|
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||
|
|
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
|
||
|
|
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||
|
|
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||
|
|
|
||
|
|
return m
|