2020-08-17 11:50:53 +08:00
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from .insn_rv32i_r_type import *
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2020-08-07 15:54:18 +08:00
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2020-08-07 16:06:15 +08:00
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"""
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OR instruction
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"""
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2020-08-07 15:54:18 +08:00
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class InsnOr(InsnRV32IRType):
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2020-08-12 13:30:12 +08:00
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b110, 0b0110011)
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2020-08-07 15:54:18 +08:00
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def elaborate(self, platform):
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2020-08-10 11:15:05 +08:00
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m = super().elaborate(platform)
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2020-08-07 15:54:18 +08:00
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata | self.rvfi_rs2_rdata, 0))
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return m
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