390 lines
15 KiB
Python
390 lines
15 KiB
Python
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from abc import abstractproperty
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from ..hdl import *
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from ..build import *
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__all__ = ["LatticeMachXO2Platform"]
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class LatticeMachXO2Platform(TemplatedPlatform):
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"""
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Required tools:
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* ``pnmainc``
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* ``ddtcmd``
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The environment is populated by running the script specified in the environment variable
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``NMIGEN_ENV_Diamond``, if present.
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Available overrides:
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* ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
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* ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
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* ``add_preferences``: inserts commands at the end of the LPF file.
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* ``add_constraints``: inserts commands at the end of the XDC file.
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Build products:
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* ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
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* ``{{name}}.jed``: JEDEC fuse file.
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* ``{{name}}.svf``: JTAG programming vector.
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"""
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toolchain = "Diamond"
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device = abstractproperty()
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package = abstractproperty()
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speed = abstractproperty()
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grade = "C" # [C]ommercial, [I]ndustrial
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required_tools = [
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"yosys",
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"pnmainc",
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"ddtcmd"
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]
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"build_{{name}}.sh": r"""
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# {{autogenerated}}
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set -e{{verbose("x")}}
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if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
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if [ -n "${{platform._toolchain_env_var}}" ]; then
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bindir=$(dirname "${{platform._toolchain_env_var}}")
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. "${{platform._toolchain_env_var}}"
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fi
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{{emit_commands("sh")}}
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""",
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_verilog()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.tcl": r"""
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prj_project new -name {{name}} -impl impl -impl_dir top_impl \
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-dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
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-lpf {{name}}.lpf \
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-synthesis synplify
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{% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
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prj_src add "{{file}}"
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{% endfor %}
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prj_src add {{name}}.v
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prj_impl option top {{name}}
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prj_src add {{name}}.sdc
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{{get_override("script_project")|default("# (script_project placeholder)")}}
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prj_project save
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prj_run Synthesis -impl impl -forceAll
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prj_run Translate -impl impl -forceAll
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prj_run Map -impl impl -forceAll
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prj_run PAR -impl impl -forceAll
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prj_run Export -impl impl -forceAll -task Jedecgen
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{{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
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""",
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"{{name}}.lpf": r"""
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# {{autogenerated}}
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BLOCK ASYNCPATHS;
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BLOCK RESETPATHS;
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{% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
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LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
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{% if extras -%}
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IOBUF PORT "{{port_name}}"
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{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
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{% endif %}
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{% endfor %}
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{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
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""",
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"{{name}}.sdc": r"""
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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{% if port_signal is not none -%}
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create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
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{% else -%}
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create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
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{% endif %}
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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""",
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}
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command_templates = [
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# These don't have any usable command-line option overrides.
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r"""
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{{invoke_tool("pnmainc")}}
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{{name}}.tcl
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""",
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r"""
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{{invoke_tool("ddtcmd")}}
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-oft -jed
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-dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
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-if {{name}}_impl/{{name}}_impl.jed -of {{name}}.jed
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""",
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r"""
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{{invoke_tool("ddtcmd")}}
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-oft -svfsingle -revd -op "FLASH Erase,Program,Verify"
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-if {{name}}_impl/{{name}}_impl.jed -of {{name}}.svf
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""",
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]
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def create_missing_domain(self, name):
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# Lattice MachXO2 devices have two global set/reset signals: PUR, which is driven at
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# startup by the configuration logic and unconditionally resets every storage element,
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# and GSR, which is driven by user logic and each storage element may be configured as
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# affected or unaffected by GSR. PUR is purely asynchronous, so even though it is
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# a low-skew global network, its deassertion may violate a setup/hold constraint with
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# relation to a user clock. To avoid this, a GSR/SGSR instance should be driven
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# synchronized to user clock.
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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else:
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rst_i = Const(0)
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gsr0 = Signal()
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gsr1 = Signal()
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m = Module()
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# There is no end-of-startup signal on MachXO2, but PUR is released after IOB enable,
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# so a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
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m.submodules += [
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Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
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Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0, o_Q=gsr1),
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# Although we already synchronize the reset input to user clock, SGSR has dedicated
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# clock routing to the center of the FPGA; use that just in case it turns out to be
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# more reliable. (None of this is documented.)
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Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
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]
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# GSR implicitly connects to every appropriate storage element. As such, the sync
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# domain is reset-less; domains driven by other clocks would need to have dedicated
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# reset circuitry or otherwise meet setup/hold constraints on their own.
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m.domains += ClockDomain("sync", reset_less=True)
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m.d.comb += ClockSignal("sync").eq(clk_i)
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return m
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_single_ended_io_types = [
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"PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12",
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"LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33",
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"LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I",
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"SSTL18_II", "HSTL18_I", "HSTL18_II",
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]
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_differential_io_types = [
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"LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E",
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"LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II",
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"HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D",
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"LVCMOS12D", "MIPI",
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]
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def should_skip_port_component(self, port, attrs, component):
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# On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
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# the PIOA or PIOC location, which is always the non-inverting pin.
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if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
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return True
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return False
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def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
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def get_ireg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("IFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_oreg(clk, d, q):
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for bit in range(len(q)):
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m.submodules += Instance("OFS1P3DX",
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i_SCLK=clk,
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i_SP=Const(1),
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i_CD=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_iddr(sclk, d, q0, q1):
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for bit in range(len(d)):
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m.submodules += Instance("IDDRXE",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_oddr(sclk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRXE",
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i_SCLK=sclk,
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i_RST=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_ineg(z, invert):
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if invert:
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a = Signal.like(z, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return a
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else:
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return z
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def get_oneg(a, invert):
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if invert:
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z = Signal.like(a, name_suffix="_n")
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m.d.comb += z.eq(~a)
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return z
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else:
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return a
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
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if "o" in pin.dir:
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o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
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if pin.dir in ("oe", "io"):
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t = Signal(1, name="{}_xdr_t".format(pin.name))
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = ~pin.oe
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elif pin.xdr == 1:
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# Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
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if "i" in pin.dir:
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get_ireg(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_oreg(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_oreg(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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get_iddr(pin.i_clk, i, pin_i0, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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# It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
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# It is not clear what is the recommended set of primitives for this task.
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# Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
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get_oreg(pin.o_clk, ~pin.oe, t)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
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i_I=port[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
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i_T=t,
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
|
||
|
|
for bit in range(len(port)):
|
||
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
|
||
|
|
i_T=t,
|
||
|
|
i_I=o[bit],
|
||
|
|
o_O=i[bit],
|
||
|
|
io_B=port[bit]
|
||
|
|
)
|
||
|
|
return m
|
||
|
|
|
||
|
|
def get_diff_input(self, pin, p_port, n_port, attrs, invert):
|
||
|
|
self._check_feature("differential input", pin, attrs,
|
||
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
||
|
|
m = Module()
|
||
|
|
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
|
||
|
|
for bit in range(len(p_port)):
|
||
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
|
||
|
|
i_I=p_port[bit],
|
||
|
|
o_O=i[bit]
|
||
|
|
)
|
||
|
|
return m
|
||
|
|
|
||
|
|
def get_diff_output(self, pin, p_port, n_port, attrs, invert):
|
||
|
|
self._check_feature("differential output", pin, attrs,
|
||
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
||
|
|
m = Module()
|
||
|
|
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||
|
|
for bit in range(len(p_port)):
|
||
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
|
||
|
|
i_I=o[bit],
|
||
|
|
o_O=p_port[bit],
|
||
|
|
)
|
||
|
|
return m
|
||
|
|
|
||
|
|
def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
|
||
|
|
self._check_feature("differential tristate", pin, attrs,
|
||
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
||
|
|
m = Module()
|
||
|
|
i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
|
||
|
|
for bit in range(len(p_port)):
|
||
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
|
||
|
|
i_T=t,
|
||
|
|
i_I=o[bit],
|
||
|
|
o_O=p_port[bit],
|
||
|
|
)
|
||
|
|
return m
|
||
|
|
|
||
|
|
def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
|
||
|
|
self._check_feature("differential input/output", pin, attrs,
|
||
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
||
|
|
m = Module()
|
||
|
|
i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
|
||
|
|
for bit in range(len(p_port)):
|
||
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
|
||
|
|
i_T=t,
|
||
|
|
i_I=o[bit],
|
||
|
|
o_O=i[bit],
|
||
|
|
io_B=p_port[bit],
|
||
|
|
)
|
||
|
|
return m
|
||
|
|
|
||
|
|
# CDC primitives are not currently specialized for MachXO2.
|