riscv-formal-nmigen/rvfi/insns/insn_divuw.py

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from .insn_rv64m_r_type import *
"""
DIVUW instruction
"""
class InsnDivuw(InsnRV64MRType):
def __init__(self, params):
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super().__init__(params, 0b101)
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def elaborate(self, platform):
m = super().elaborate(platform)
result = Signal(32)
if self.params.altops:
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0x8c629acb10e8fd70)
else:
m.d.comb += result.eq(Mux(self.rvfi_rs2_rdata[:32] == 0, 2 ** 32 - 1, self.rvfi_rs1_rdata[:32] // self.rvfi_rs2_rdata[:32]))
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
return m