2020-08-27 15:48:11 +08:00
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from .insn_rv64i_r_type import *
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"""
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ADDW instruction
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"""
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class InsnAddw(InsnRV64IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b000)
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2020-08-28 12:30:39 +08:00
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2020-08-27 15:48:11 +08:00
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def elaborate(self, platform):
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m = super().elaborate(platform)
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result = Signal(32)
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m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] + self.rvfi_rs2_rdata[:32])
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m.d.comb += spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
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return m
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