riscv-formal-nmigen/rvfi/checks/pc_fwd_check.py

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2020-08-19 17:00:11 +08:00
from nmigen import *
from nmigen.asserts import *
"""
PC Forward Check
"""
class PcFwdCheck(Elaboratable):
def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
# Core-specific constants
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
# Address validity and equality
self.rvformal_addr_valid = rvformal_addr_valid
self.rvformal_addr_eq = lambda a, b: (self.rvformal_addr_valid(a) == self.rvformal_addr_valid(b)) & ((~self.rvformal_addr_valid(a)) | (a == b))
# Input ports
self.reset = Signal(1)
self.check = Signal(1)
self.rvfi_valid = Signal(1)
self.rvfi_order = Signal(64)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.reset,
self.check,
self.rvfi_valid,
self.rvfi_order,
self.rvfi_pc_rdata,
self.rvfi_pc_wdata
]
return input_ports
def elaborate(self, platform):
m = Module()
insn_order = AnyConst(64)
expect_pc = Signal(self.RISCV_FORMAL_XLEN)
expect_pc_valid = Signal(1, reset=0)
pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
with m.If(self.reset):
m.d.sync += expect_pc_valid.eq(0)
with m.Else():
with m.If(self.check):
m.d.comb += Assume(self.rvfi_valid)
m.d.comb += Assume(insn_order == self.rvfi_order)
with m.If(expect_pc_valid):
m.d.comb += Assert(self.rvformal_addr_eq(expect_pc, pc_rdata))
with m.Else():
with m.If(self.rvfi_valid & (self.rvfi_order == insn_order - 1)):
m.d.sync += expect_pc.eq(self.rvfi_pc_wdata)
m.d.sync += expect_pc_valid.eq(1)
return m