2020-08-28 11:55:11 +08:00
|
|
|
from .insn_rv64m_r_type import *
|
|
|
|
|
|
|
|
|
|
"""
|
|
|
|
|
DIVUW instruction
|
|
|
|
|
"""
|
|
|
|
|
|
|
|
|
|
class InsnDivuw(InsnRV64MRType):
|
|
|
|
|
def __init__(self, params):
|
2020-08-28 12:20:56 +08:00
|
|
|
super().__init__(params, 0b101)
|
2020-08-28 12:30:39 +08:00
|
|
|
|
2020-08-28 11:55:11 +08:00
|
|
|
def elaborate(self, platform):
|
|
|
|
|
m = super().elaborate(platform)
|
|
|
|
|
|
|
|
|
|
result = Signal(32)
|
|
|
|
|
if self.params.altops:
|
|
|
|
|
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0x8c629acb10e8fd70)
|
|
|
|
|
else:
|
|
|
|
|
m.d.comb += result.eq(Mux(self.rvfi_rs2_rdata[:32] == 0, 2 ** 32 - 1, self.rvfi_rs1_rdata[:32] // self.rvfi_rs2_rdata[:32]))
|
|
|
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
|
|
|
|
|
|
|
|
|
|
return m
|
