riscv-formal-nmigen/rvfi/insns/insn_andi.py

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from .insn_rv32i_i_type_arith import *
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"""
ANDI instruction
"""
class InsnAndi(InsnRV32IITypeArith):
def __init__(self, params):
super().__init__(params, 0b111)
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def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.insn_imm, 0))
return m