92 lines
4.3 KiB
Markdown
92 lines
4.3 KiB
Markdown
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# Minerva
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## A 32-bit RISC-V soft processor
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Minerva is a CPU core that currently implements the [RISC-V][1] RV32IM instruction set. Its microarchitecture is described in plain Python code using the [nMigen][2] toolbox.
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### Quick start
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Minerva currently requires Python 3.6+ and [nMigen][2] on its `master` branch.
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python setup.py install
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python cli.py generate > minerva.v
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To use Minerva in its minimal configuration, you need to wire the following ports to `minerva_cpu`:
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* `clk`
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* `rst`
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* `ibus__*`
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* `dbus__*`
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* `external_interrupt`
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* `timer_interrupt`
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* `software_interrupt`
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### Features
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The microarchitecture of Minerva is largely inspired by the [LatticeMico32][3] processor.
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Minerva is pipelined on 6 stages:
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1. **Address**
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The address of the next instruction is calculated and sent to the instruction cache.
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2. **Fetch**
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The instruction is read from memory.
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3. **Decode**
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The instruction is decoded, and operands are either fetched from the register file or bypassed from the pipeline. Branches are predicted by the static branch predictor.
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4. **Execute**
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Simple instructions such as arithmetic and logical operations are completed at this stage.
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5. **Memory**
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More complicated instructions such as loads, stores and shifts require a second execution stage.
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6. **Writeback**
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Results produced by the instructions are written back to the register file.
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The L1 data cache is coupled to a write buffer. Store transactions are in this case done to the write buffer instead of the data bus. This enables stores to proceed in one clock cycle if the buffer isn't full, without having to wait for the bus transaction to complete. Store transactions are then completed in the background as the write buffer gets emptied to the data bus.
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### Configuration
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The following parameters can be used to configure the Minerva core.
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| Parameter | Default value | Description |
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| ----------------- | -------------- | -------------------------------------------------- |
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| `reset_address` | `0x00000000` | Reset vector address |
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| `with_icache` | `False` | Enable the instruction cache |
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| `icache_nways` | `1` | Number of ways in the instruction cache |
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| `icache_nlines` | `128` | Number of lines in the instruction cache |
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| `icache_nwords` | `4` | Number of words in a line of the instruction cache |
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| `icache_base` | `0x00000000` | Base of the instruction cache address space |
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| `icache_limit` | `0x80000000` | Limit of the instruction cache address space |
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| `with_dcache` | `False` | Enable the data cache |
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| `dcache_nways` | `1` | Number of ways in the data cache |
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| `dcache_nlines` | `128` | Number of lines in the data cache |
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| `dcache_nwords` | `4` | Number of words in a line of the data cache |
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| `dcache_base` | `0x00000000` | Base of the data cache address space |
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| `dcache_limit` | `0x80000000` | Limit of the data cache address space |
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| `with_muldiv` | `False` | Enable RV32M support |
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| `with_debug` | `False` | Enable the Debug Module |
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| `with_trigger` | `False` | Enable the Trigger Module |
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| `nb_triggers` | `8` | Number of triggers |
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| `with_rvfi` | `False` | Enable the riscv-formal interface |
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### Possible improvements
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In no particular order:
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* RV64I
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* Floating Point Unit
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* Stateful branch prediction
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* MMU
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* ...
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If you are interested in sponsoring new features or improvements, get in touch at contact [at] lambdaconcept.com .
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### License
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Minerva is released under the permissive two-clause BSD license.
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See LICENSE file for full copyright and license information.
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[1]: https://riscv.org/specifications/
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[2]: https://github.com/m-labs/nmigen/
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[3]: https://github.com/m-labs/lm32/
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