73 lines
2.0 KiB
Python
73 lines
2.0 KiB
Python
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from nmigen import *
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from nmigen.hdl.rec import *
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from nmigen.lib.coding import *
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__all__ = ["Cycle", "wishbone_layout", "WishboneArbiter"]
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class Cycle:
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CLASSIC = 0
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CONSTANT = 1
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INCREMENT = 2
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END = 7
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wishbone_layout = [
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("adr", 30, DIR_FANOUT),
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("dat_w", 32, DIR_FANOUT),
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("dat_r", 32, DIR_FANIN),
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("sel", 4, DIR_FANOUT),
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("cyc", 1, DIR_FANOUT),
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("stb", 1, DIR_FANOUT),
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("ack", 1, DIR_FANIN),
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("we", 1, DIR_FANOUT),
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("cti", 3, DIR_FANOUT),
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("bte", 2, DIR_FANOUT),
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("err", 1, DIR_FANIN)
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]
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class WishboneArbiter(Elaboratable):
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def __init__(self):
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self.bus = Record(wishbone_layout)
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self._port_map = dict()
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def port(self, priority):
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if not isinstance(priority, int) or priority < 0:
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raise TypeError("Priority must be a non-negative integer, not '{!r}'"
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.format(priority))
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if priority in self._port_map:
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raise ValueError("Conflicting priority: '{!r}'".format(priority))
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port = self._port_map[priority] = Record.like(self.bus)
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return port
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def elaborate(self, platform):
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m = Module()
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ports = [port for priority, port in sorted(self._port_map.items())]
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for port in ports:
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m.d.comb += port.dat_r.eq(self.bus.dat_r)
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bus_pe = m.submodules.bus_pe = PriorityEncoder(len(ports))
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with m.If(~self.bus.cyc):
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for j, port in enumerate(ports):
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m.d.sync += bus_pe.i[j].eq(port.cyc)
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source = Array(ports)[bus_pe.o]
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m.d.comb += [
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self.bus.adr.eq(source.adr),
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self.bus.dat_w.eq(source.dat_w),
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self.bus.sel.eq(source.sel),
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self.bus.cyc.eq(source.cyc),
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self.bus.stb.eq(source.stb),
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self.bus.we.eq(source.we),
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self.bus.cti.eq(source.cti),
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self.bus.bte.eq(source.bte),
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source.ack.eq(self.bus.ack),
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source.err.eq(self.bus.err)
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]
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return m
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