122 lines
5.1 KiB
Python
122 lines
5.1 KiB
Python
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from nmigen import *
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from nmigen.lib.coding import PriorityEncoder
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from ..csr import *
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from ..isa import *
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__all__ = ["ExceptionUnit"]
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class ExceptionUnit(Elaboratable, AutoCSR):
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def __init__(self):
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self.mstatus = CSR(0x300, mstatus_layout)
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self.misa = CSR(0x301, misa_layout) # FIXME move elsewhere
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self.mie = CSR(0x304, mie_layout)
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self.mtvec = CSR(0x305, mtvec_layout)
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self.mscratch = CSR(0x340, flat_layout) # FIXME move elsewhere
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self.mepc = CSR(0x341, mepc_layout)
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self.mcause = CSR(0x342, mcause_layout)
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self.mtval = CSR(0x343, flat_layout)
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self.mip = CSR(0x344, mip_layout)
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self.irq_mask = CSR(0x330, flat_layout)
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self.irq_pending = CSR(0x360, flat_layout)
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self.external_interrupt = Signal(32)
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self.timer_interrupt = Signal()
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self.software_interrupt = Signal()
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self.m_fetch_misaligned = Signal()
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self.m_fetch_error = Signal()
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self.m_fetch_badaddr = Signal(30)
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self.m_load_misaligned = Signal()
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self.m_load_error = Signal()
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self.m_store_misaligned = Signal()
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self.m_store_error = Signal()
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self.m_loadstore_badaddr = Signal(30)
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self.m_branch_target = Signal(32)
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self.m_illegal = Signal()
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self.m_ebreak = Signal()
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self.m_ecall = Signal()
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self.m_pc = Signal(32)
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self.m_instruction = Signal(32)
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self.m_result = Signal(32)
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self.m_mret = Signal()
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self.m_stall = Signal()
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self.m_valid = Signal()
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self.m_raise = Signal()
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def elaborate(self, platform):
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m = Module()
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for csr in self.iter_csrs():
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with m.If(csr.we):
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m.d.sync += csr.r.eq(csr.w)
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trap_pe = m.submodules.trap_pe = PriorityEncoder(16)
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m.d.comb += [
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trap_pe.i[Cause.FETCH_MISALIGNED ].eq(self.m_fetch_misaligned),
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trap_pe.i[Cause.FETCH_ACCESS_FAULT ].eq(self.m_fetch_error),
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trap_pe.i[Cause.ILLEGAL_INSTRUCTION].eq(self.m_illegal),
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trap_pe.i[Cause.BREAKPOINT ].eq(self.m_ebreak),
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trap_pe.i[Cause.LOAD_MISALIGNED ].eq(self.m_load_misaligned),
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trap_pe.i[Cause.LOAD_ACCESS_FAULT ].eq(self.m_load_error),
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trap_pe.i[Cause.STORE_MISALIGNED ].eq(self.m_store_misaligned),
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trap_pe.i[Cause.STORE_ACCESS_FAULT ].eq(self.m_store_error),
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trap_pe.i[Cause.ECALL_FROM_M ].eq(self.m_ecall)
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]
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m.d.sync += [
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self.irq_pending.r.eq(self.external_interrupt & self.irq_mask.r),
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self.mip.r.msip.eq(self.software_interrupt),
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self.mip.r.mtip.eq(self.timer_interrupt),
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self.mip.r.meip.eq(self.irq_pending.r.bool())
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]
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interrupt_pe = m.submodules.interrupt_pe = PriorityEncoder(16)
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m.d.comb += [
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interrupt_pe.i[Cause.M_SOFTWARE_INTERRUPT].eq(self.mip.r.msip & self.mie.r.msie),
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interrupt_pe.i[Cause.M_TIMER_INTERRUPT ].eq(self.mip.r.mtip & self.mie.r.mtie),
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interrupt_pe.i[Cause.M_EXTERNAL_INTERRUPT].eq(self.mip.r.meip & self.mie.r.meie)
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]
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m.d.comb += self.m_raise.eq(~trap_pe.n | ~interrupt_pe.n & self.mstatus.r.mie)
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with m.If(self.m_valid & ~self.m_stall):
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with m.If(self.m_raise):
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m.d.sync += [
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self.mstatus.r.mpie.eq(self.mstatus.r.mie),
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self.mstatus.r.mie.eq(0),
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self.mepc.r.base.eq(self.m_pc[2:])
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]
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with m.If(~trap_pe.n):
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m.d.sync += [
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self.mcause.r.ecode.eq(trap_pe.o),
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self.mcause.r.interrupt.eq(0)
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]
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with m.Switch(trap_pe.o):
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with m.Case(Cause.FETCH_MISALIGNED):
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m.d.sync += self.mtval.r.eq(self.m_branch_target)
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with m.Case(Cause.FETCH_ACCESS_FAULT):
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m.d.sync += self.mtval.r.eq(self.m_fetch_badaddr << 2)
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with m.Case(Cause.ILLEGAL_INSTRUCTION):
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m.d.sync += self.mtval.r.eq(self.m_instruction)
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with m.Case(Cause.BREAKPOINT):
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m.d.sync += self.mtval.r.eq(self.m_pc)
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with m.Case(Cause.LOAD_MISALIGNED, Cause.STORE_MISALIGNED):
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m.d.sync += self.mtval.r.eq(self.m_result)
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with m.Case(Cause.LOAD_ACCESS_FAULT, Cause.STORE_ACCESS_FAULT):
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m.d.sync += self.mtval.r.eq(self.m_loadstore_badaddr << 2)
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with m.Case():
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m.d.sync += self.mtval.r.eq(0)
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with m.Else():
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m.d.sync += [
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self.mcause.r.ecode.eq(interrupt_pe.o),
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self.mcause.r.interrupt.eq(1)
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]
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with m.Elif(self.m_mret):
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m.d.sync += self.mstatus.r.mie.eq(self.mstatus.r.mpie)
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return m
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