2020-07-23 12:42:59 +08:00
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with open('isa_rv32i.py', 'w') as isa_rv32i:
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def fprint(strng):
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print(strng, file=isa_rv32i)
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fprint("# Generated by isa_rv32i_gen.py")
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fprint("from nmigen import *")
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fprint("")
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fprint("class rvfi_isa_rv32i(Elaboratable):")
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fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):")
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fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN")
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fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN")
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fprint(" self.rvfi_valid = Signal(1)")
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fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)")
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fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint("")
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fprint(" self.spec_valid = Signal(1)")
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fprint(" self.spec_trap = Signal(1)")
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fprint(" self.spec_rs1_addr = Signal(5)")
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fprint(" self.spec_rs2_addr = Signal(5)")
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fprint(" self.spec_rd_addr = Signal(5)")
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fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
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fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
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fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)")
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fprint(" def ports(self):")
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fprint(" input_ports = [")
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fprint(" self.rvfi_valid,")
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fprint(" self.rvfi_insn,")
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fprint(" self.rvfi_pc_rdata,")
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fprint(" self.rvfi_rs1_rdata,")
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fprint(" self.rvfi_rs2_rdata,")
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fprint(" self.rvfi_mem_rdata")
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fprint(" ]")
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fprint(" output_ports = [")
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fprint(" self.spec_valid,")
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fprint(" self.spec_trap,")
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fprint(" self.spec_rs1_addr,")
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fprint(" self.spec_rs2_addr,")
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fprint(" self.spec_rd_addr,")
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fprint(" self.spec_rd_wdata,")
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fprint(" self.spec_pc_wdata,")
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fprint(" self.spec_mem_addr,")
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fprint(" self.spec_mem_rmask,")
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fprint(" self.spec_mem_wmask,")
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fprint(" self.spec_mem_wdata")
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fprint(" ]")
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2020-07-23 12:57:32 +08:00
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fprint(" return input_ports + output_ports")
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2020-07-23 12:42:59 +08:00
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fprint(" def elaborate(self, platform):")
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fprint(" m = Module()")
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fprint("")
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# TODO
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fprint("")
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fprint(" return m")
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# For debugging purposes only
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fprint("")
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fprint("test = rvfi_isa_rv32i()")
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fprint("test.ports()")
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fprint("test.elaborate(platform=None)")
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