216 lines
6.0 KiB
Python
216 lines
6.0 KiB
Python
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from .csr import *
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class Opcode:
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LUI = 0b01101
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AUIPC = 0b00101
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JAL = 0b11011
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JALR = 0b11001
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BRANCH = 0b11000
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LOAD = 0b00000
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STORE = 0b01000
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OP_IMM_32 = 0b00100
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OP_32 = 0b01100
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MISC_MEM = 0b00011
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SYSTEM = 0b11100
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class Funct3:
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BEQ = B = ADD = FENCE = PRIV = MUL = 0b000
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BNE = H = SLL = FENCEI = CSRRW = MULH = 0b001
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_ = W = SLT = _ = CSRRS = MULHSU = 0b010
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_ = _ = SLTU = _ = CSRRC = MULHU = 0b011
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BLT = BU = XOR = _ = _ = DIV = 0b100
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BGE = HU = SR = _ = CSRRWI = DIVU = 0b101
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BLTU = _ = OR = _ = CSRRSI = REM = 0b110
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BGEU = _ = AND = _ = CSRRCI = REMU = 0b111
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class Funct7:
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SRL = ADD = 0b0000000
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MULDIV = 0b0000001
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SRA = SUB = 0b0100000
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class Funct12:
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ECALL = 0b000000000000
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EBREAK = 0b000000000001
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MRET = 0b001100000010
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WFI = 0b000100000101
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class CSRIndex:
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MVENDORID = 0xF11
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MARCHID = 0xF12
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MIMPID = 0xF13
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MHARTID = 0xF14
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MSTATUS = 0x300
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MISA = 0x301
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MEDELEG = 0x302
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MIDELEG = 0x303
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MIE = 0x304
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MTVEC = 0x305
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MCOUTEREN = 0x306
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MSCRATCH = 0x340
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MEPC = 0x341
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MCAUSE = 0x342
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MTVAL = 0x343
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MIP = 0x344
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# µarch specific
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IRQ_MASK = 0x330
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IRQ_PENDING = 0x360
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# trigger module
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TSELECT = 0x7a0
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TDATA1 = 0x7a1
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TDATA2 = 0x7a2
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TDATA3 = 0x7a3
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TINFO = 0x7a4
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MCONTEXT = 0x7a8
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# debug module
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DCSR = 0x7b0
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DPC = 0x7b1
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class Cause:
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FETCH_MISALIGNED = 0
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FETCH_ACCESS_FAULT = 1
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ILLEGAL_INSTRUCTION = 2
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BREAKPOINT = 3
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LOAD_MISALIGNED = 4
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LOAD_ACCESS_FAULT = 5
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STORE_MISALIGNED = 6
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STORE_ACCESS_FAULT = 7
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ECALL_FROM_U = 8
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ECALL_FROM_S = 9
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ECALL_FROM_M = 11
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FETCH_PAGE_FAULT = 12
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LOAD_PAGE_FAULT = 13
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STORE_PAGE_FAULT = 15
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# interrupts
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U_SOFTWARE_INTERRUPT = 0
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S_SOFTWARE_INTERRUPT = 1
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M_SOFTWARE_INTERRUPT = 3
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U_TIMER_INTERRUPT = 4
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S_TIMER_INTERRUPT = 5
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M_TIMER_INTERRUPT = 7
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U_EXTERNAL_INTERRUPT = 8
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S_EXTERNAL_INTERRUPT = 9
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M_EXTERNAL_INTERRUPT = 11
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# CSR layouts
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flat_layout = [
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("value", 32, CSRAccess.RW),
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]
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misa_layout = [
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("extensions", 26, CSRAccess.RW),
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("zero", 4, CSRAccess.RO),
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("mxl", 2, CSRAccess.RW),
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]
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mstatus_layout = [
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("uie", 1, CSRAccess.RO), # User Interrupt Enable
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("sie", 1, CSRAccess.RO), # Supervisor Interrupt Enable
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("zero0", 1, CSRAccess.RO),
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("mie", 1, CSRAccess.RW), # Machine Interrupt Enable
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("upie", 1, CSRAccess.RO), # User Previous Interrupt Enable
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("spie", 1, CSRAccess.RO), # Supervisor Previous Interrupt Enable
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("zero1", 1, CSRAccess.RO),
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("mpie", 1, CSRAccess.RW), # Machine Previous Interrupt Enable
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("spp", 1, CSRAccess.RO), # Supervisor Previous Privilege
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("zero2", 2, CSRAccess.RO),
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("mpp", 2, CSRAccess.RW), # Machine Previous Privilege
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("fs", 2, CSRAccess.RO), # FPU Status
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("xs", 2, CSRAccess.RO), # user-mode eXtensions Status
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("mprv", 1, CSRAccess.RO), # Modify PRiVilege
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("sum", 1, CSRAccess.RO), # Supervisor User Memory access
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("mxr", 1, CSRAccess.RO), # Make eXecutable Readable
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("tvm", 1, CSRAccess.RO), # Trap Virtual Memory
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("tw", 1, CSRAccess.RO), # Timeout Wait
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("tsr", 1, CSRAccess.RO), # Trap SRET
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("zero3", 8, CSRAccess.RO),
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("sd", 1, CSRAccess.RO), # State Dirty (set if XS or FS are set to dirty)
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]
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mtvec_layout = [
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("mode", 2, CSRAccess.RW),
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("base", 30, CSRAccess.RW),
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]
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mepc_layout = [
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("zero", 2, CSRAccess.RO), # 16-bit instructions are not supported
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("base", 30, CSRAccess.RW),
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]
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mip_layout = [
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("usip", 1, CSRAccess.RO),
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("ssip", 1, CSRAccess.RO),
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("zero0", 1, CSRAccess.RO),
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("msip", 1, CSRAccess.RW),
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("utip", 1, CSRAccess.RO),
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("stip", 1, CSRAccess.RO),
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("zero1", 1, CSRAccess.RO),
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("mtip", 1, CSRAccess.RW),
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("ueip", 1, CSRAccess.RO),
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("seip", 1, CSRAccess.RO),
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("zero2", 1, CSRAccess.RO),
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("meip", 1, CSRAccess.RW),
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("zero3", 20, CSRAccess.RO),
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]
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mie_layout = [
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("usie", 1, CSRAccess.RO),
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("ssie", 1, CSRAccess.RO),
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("zero0", 1, CSRAccess.RO),
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("msie", 1, CSRAccess.RW),
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("utie", 1, CSRAccess.RO),
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("stie", 1, CSRAccess.RO),
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("zero1", 1, CSRAccess.RO),
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("mtie", 1, CSRAccess.RW),
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("ueie", 1, CSRAccess.RO),
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("seie", 1, CSRAccess.RO),
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("zero2", 1, CSRAccess.RO),
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("meie", 1, CSRAccess.RW),
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("zero3", 20, CSRAccess.RO),
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]
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mcause_layout = [
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("ecode", 31, CSRAccess.RW),
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("interrupt", 1, CSRAccess.RW),
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]
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dcsr_layout = [
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("prv", 2, CSRAccess.RW), # Privilege level before Debug Mode was entered
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("step", 1, CSRAccess.RW), # Execute a single instruction and re-enter Debug Mode
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("nmip", 1, CSRAccess.RO), # A non-maskable interrupt is pending
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("mprven", 1, CSRAccess.RW), # Use mstatus.mprv in Debug Mode
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("zero0", 1, CSRAccess.RO),
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("cause", 3, CSRAccess.RO), # Explains why Debug Mode was entered
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("stoptime", 1, CSRAccess.RW), # Stop timer increment during Debug Mode
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("stopcount", 1, CSRAccess.RW), # Stop counter increment during Debug Mode
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("stepie", 1, CSRAccess.RW), # Enable interrupts during single stepping
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("ebreaku", 1, CSRAccess.RW), # EBREAKs in U-mode enter Debug Mode
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("ebreaks", 1, CSRAccess.RW), # EBREAKs in S-mode enter Debug Mode
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("zero1", 1, CSRAccess.RO),
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("ebreakm", 1, CSRAccess.RW), # EBREAKs in M-mode enter Debug Mode
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("zero2", 12, CSRAccess.RO),
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("xdebugver", 4, CSRAccess.RO), # External Debug specification version
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]
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tdata1_layout = [
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("data", 27, CSRAccess.RW),
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("dmode", 1, CSRAccess.RW),
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("type", 4, CSRAccess.RW),
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]
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