179 lines
6.9 KiB
Python
179 lines
6.9 KiB
Python
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from nmigen import *
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from nmigen.asserts import *
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from nmigen.lib.coding import Encoder
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from nmigen.utils import log2_int
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__all__ = ["L1Cache"]
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class L1Cache(Elaboratable):
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def __init__(self, nways, nlines, nwords, base, limit):
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if not isinstance(nlines, int):
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raise TypeError("nlines must be an integer, not {!r}".format(nlines))
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if nlines == 0 or nlines & nlines - 1:
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raise ValueError("nlines must be a power of 2, not {}".format(nlines))
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if nwords not in {4, 8, 16}:
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raise ValueError("nwords must be 4, 8 or 16, not {!r}".format(nwords))
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if nways not in {1, 2}:
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raise ValueError("nways must be 1 or 2, not {!r}".format(nways))
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if not isinstance(base, int):
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raise TypeError("base must be an integer, not {!r}".format(base))
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if base not in range(0, 2**32) or base & base - 1:
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raise ValueError("base must be 0 or a power of 2 (< 2**32), not {:#x}".format(base))
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if not isinstance(limit, int):
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raise TypeError("limit must be an integer, not {!r}".format(limit))
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if limit not in range(1, 2**32 + 1) or limit & limit - 1:
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raise ValueError("limit must be a power of 2 (<= 2**32), not {:#x}".format(limit))
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if base >= limit:
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raise ValueError("limit {:#x} must be greater than base {:#x}"
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.format(limit, base))
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self.nways = nways
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self.nlines = nlines
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self.nwords = nwords
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self.base = base
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self.limit = limit
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offsetbits = log2_int(nwords)
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linebits = log2_int(nlines)
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tagbits = log2_int(limit) - linebits - offsetbits - 2
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self.s1_addr = Record([("offset", offsetbits), ("line", linebits), ("tag", tagbits)])
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self.s1_stall = Signal()
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self.s1_valid = Signal()
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self.s2_addr = Record.like(self.s1_addr)
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self.s2_re = Signal()
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self.s2_flush = Signal()
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self.s2_evict = Signal()
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self.s2_valid = Signal()
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self.bus_valid = Signal()
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self.bus_error = Signal()
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self.bus_rdata = Signal(32)
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self.s2_miss = Signal()
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self.s2_flush_ack = Signal()
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self.s2_rdata = Signal(32)
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self.bus_re = Signal()
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self.bus_addr = Record.like(self.s1_addr)
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self.bus_last = Signal()
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def elaborate(self, platform):
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m = Module()
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ways = Array(Record([("data", self.nwords * 32),
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("tag", self.s2_addr.tag.shape()),
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("valid", 1),
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("bus_re", 1)])
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for _ in range(self.nways))
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if self.nways == 1:
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way_lru = Const(0)
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elif self.nways == 2:
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way_lru = Signal()
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with m.If(self.bus_re & self.bus_valid & self.bus_last & ~self.bus_error):
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m.d.sync += way_lru.eq(~way_lru)
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m.d.comb += ways[way_lru].bus_re.eq(self.bus_re)
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way_hit = m.submodules.way_hit = Encoder(self.nways)
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for j, way in enumerate(ways):
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m.d.comb += way_hit.i[j].eq((way.tag == self.s2_addr.tag) & way.valid)
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m.d.comb += [
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self.s2_miss.eq(way_hit.n),
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self.s2_rdata.eq(ways[way_hit.o].data.word_select(self.s2_addr.offset, 32))
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]
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flush_line = Signal(range(self.nlines), reset=self.nlines - 1)
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with m.If(self.s1_valid & ~self.s1_stall):
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m.d.sync += self.s2_flush_ack.eq(0)
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with m.FSM() as fsm:
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last_offset = Signal.like(self.s2_addr.offset)
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with m.State("CHECK"):
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with m.If(self.s2_valid):
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with m.If(self.s2_flush & ~self.s2_flush_ack):
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m.d.sync += flush_line.eq(flush_line.reset)
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m.next = "FLUSH"
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with m.Elif(self.s2_re & self.s2_miss):
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m.d.sync += [
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self.bus_addr.eq(self.s2_addr),
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self.bus_re.eq(1),
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last_offset.eq(self.s2_addr.offset - 1)
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]
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m.next = "REFILL"
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with m.State("REFILL"):
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m.d.comb += self.bus_last.eq(self.bus_addr.offset == last_offset)
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with m.If(self.bus_valid):
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m.d.sync += self.bus_addr.offset.eq(self.bus_addr.offset + 1)
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with m.If(self.bus_valid & self.bus_last | self.bus_error):
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m.d.sync += self.bus_re.eq(0)
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with m.If(~self.bus_re & ~self.s1_stall):
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m.next = "CHECK"
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with m.State("FLUSH"):
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with m.If(flush_line == 0):
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m.d.sync += self.s2_flush_ack.eq(1)
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m.next = "CHECK"
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with m.Else():
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m.d.sync += flush_line.eq(flush_line - 1)
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if platform == "formal":
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with m.If(Initial()):
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m.d.comb += Assume(fsm.ongoing("CHECK"))
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for way in ways:
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tag_mem = Memory(width=1 + len(way.tag), depth=self.nlines)
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tag_rp = tag_mem.read_port()
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tag_wp = tag_mem.write_port()
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m.submodules += tag_rp, tag_wp
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data_mem = Memory(width=len(way.data), depth=self.nlines)
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data_rp = data_mem.read_port()
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data_wp = data_mem.write_port(granularity=32)
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m.submodules += data_rp, data_wp
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mem_rp_addr = Signal.like(self.s1_addr.line)
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with m.If(self.s1_stall):
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m.d.comb += mem_rp_addr.eq(self.s2_addr.line)
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with m.Else():
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m.d.comb += mem_rp_addr.eq(self.s1_addr.line)
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m.d.comb += [
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tag_rp.addr.eq(mem_rp_addr),
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data_rp.addr.eq(mem_rp_addr),
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Cat(way.tag, way.valid).eq(tag_rp.data),
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way.data.eq(data_rp.data),
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]
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with m.If(fsm.ongoing("FLUSH")):
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m.d.comb += [
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tag_wp.addr.eq(flush_line),
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tag_wp.en.eq(1),
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tag_wp.data.eq(0),
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]
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with m.Elif(way.bus_re):
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m.d.comb += [
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tag_wp.addr.eq(self.bus_addr.line),
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tag_wp.en.eq(way.bus_re & self.bus_valid),
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tag_wp.data.eq(Cat(self.bus_addr.tag, self.bus_last & ~self.bus_error)),
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]
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with m.Else():
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m.d.comb += [
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tag_wp.addr.eq(self.s2_addr.line),
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tag_wp.en.eq(self.s2_evict & self.s2_valid & (way.tag == self.s2_addr.tag)),
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tag_wp.data.eq(0),
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]
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m.d.comb += [
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data_wp.addr.eq(self.bus_addr.line),
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data_wp.en.bit_select(self.bus_addr.offset, 1).eq(way.bus_re & self.bus_valid),
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data_wp.data.eq(Repl(self.bus_rdata, self.nwords)),
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]
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return m
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