198 lines
6.6 KiB
Python
198 lines
6.6 KiB
Python
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from functools import reduce
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from operator import or_
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from nmigen import *
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from nmigen.hdl.rec import *
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from ..isa import *
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from ..wishbone import *
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__all__ = ["rvfi_layout", "RVFIController"]
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# RISC-V Formal Interface
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# https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md
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rvfi_layout = [
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("valid", 1, DIR_FANOUT),
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("order", 64, DIR_FANOUT),
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("insn", 32, DIR_FANOUT),
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("trap", 1, DIR_FANOUT),
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("halt", 1, DIR_FANOUT),
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("intr", 1, DIR_FANOUT),
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("mode", 2, DIR_FANOUT),
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("ixl", 2, DIR_FANOUT),
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("rs1_addr", 5, DIR_FANOUT),
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("rs2_addr", 5, DIR_FANOUT),
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("rs1_rdata", 32, DIR_FANOUT),
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("rs2_rdata", 32, DIR_FANOUT),
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("rd_addr", 5, DIR_FANOUT),
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("rd_wdata", 32, DIR_FANOUT),
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("pc_rdata", 32, DIR_FANOUT),
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("pc_wdata", 32, DIR_FANOUT),
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("mem_addr", 32, DIR_FANOUT),
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("mem_rmask", 4, DIR_FANOUT),
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("mem_wmask", 4, DIR_FANOUT),
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("mem_rdata", 32, DIR_FANOUT),
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("mem_wdata", 32, DIR_FANOUT)
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]
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class RVFIController(Elaboratable):
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def __init__(self):
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self.rvfi = Record(rvfi_layout)
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self.d_insn = Signal.like(self.rvfi.insn)
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self.d_rs1_addr = Signal.like(self.rvfi.rs1_addr)
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self.d_rs2_addr = Signal.like(self.rvfi.rs2_addr)
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self.d_rs1_rdata = Signal.like(self.rvfi.rs1_rdata)
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self.d_rs2_rdata = Signal.like(self.rvfi.rs2_rdata)
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self.d_stall = Signal()
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self.x_mem_addr = Signal.like(self.rvfi.mem_addr)
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self.x_mem_wmask = Signal.like(self.rvfi.mem_wmask)
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self.x_mem_rmask = Signal.like(self.rvfi.mem_rmask)
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self.x_mem_wdata = Signal.like(self.rvfi.mem_wdata)
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self.x_stall = Signal()
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self.m_mem_rdata = Signal.like(self.rvfi.mem_rdata)
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self.m_fetch_misaligned = Signal()
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self.m_illegal_insn = Signal()
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self.m_load_misaligned = Signal()
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self.m_store_misaligned = Signal()
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self.m_exception = Signal()
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self.m_mret = Signal()
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self.m_branch_taken = Signal()
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self.m_branch_target = Signal(32)
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self.m_pc_rdata = Signal.like(self.rvfi.pc_rdata)
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self.m_stall = Signal()
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self.m_valid = Signal()
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self.w_rd_addr = Signal.like(self.rvfi.rd_addr)
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self.w_rd_wdata = Signal.like(self.rvfi.rd_wdata)
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self.mtvec_r_base = Signal(30)
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self.mepc_r_value = Signal(32)
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def elaborate(self, platform):
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m = Module()
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# Instruction Metadata
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with m.If(~self.m_stall):
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m.d.sync += self.rvfi.valid.eq(self.m_valid)
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with m.Elif(self.rvfi.valid):
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m.d.sync += self.rvfi.valid.eq(0)
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with m.If(self.rvfi.valid):
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m.d.sync += self.rvfi.order.eq(self.rvfi.order + 1)
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x_insn = Signal.like(self.rvfi.insn)
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m_insn = Signal.like(self.rvfi.insn)
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with m.If(~self.d_stall):
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m.d.sync += x_insn.eq(self.d_insn)
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with m.If(~self.x_stall):
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m.d.sync += m_insn.eq(x_insn)
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with m.If(~self.m_stall):
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m.d.sync += self.rvfi.insn.eq(m_insn)
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with m.If(~self.m_stall):
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m.d.sync += [
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self.rvfi.trap.eq(reduce(or_, (
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self.m_fetch_misaligned,
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self.m_illegal_insn,
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self.m_load_misaligned,
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self.m_store_misaligned
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))),
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self.rvfi.intr.eq(self.m_pc_rdata == self.mtvec_r_base << 2)
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]
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m.d.comb += [
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self.rvfi.mode.eq(Const(3)), # M-mode
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self.rvfi.ixl.eq(Const(1)) # XLEN=32
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]
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# Integer Register Read/Write
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x_rs1_addr = Signal.like(self.rvfi.rs1_addr)
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x_rs2_addr = Signal.like(self.rvfi.rs2_addr)
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x_rs1_rdata = Signal.like(self.rvfi.rs1_rdata)
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x_rs2_rdata = Signal.like(self.rvfi.rs2_rdata)
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m_rs1_addr = Signal.like(self.rvfi.rs1_addr)
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m_rs2_addr = Signal.like(self.rvfi.rs2_addr)
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m_rs1_rdata = Signal.like(self.rvfi.rs1_rdata)
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m_rs2_rdata = Signal.like(self.rvfi.rs2_rdata)
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with m.If(~self.d_stall):
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m.d.sync += [
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x_rs1_addr.eq(self.d_rs1_addr),
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x_rs2_addr.eq(self.d_rs2_addr),
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x_rs1_rdata.eq(self.d_rs1_rdata),
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x_rs2_rdata.eq(self.d_rs2_rdata)
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]
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with m.If(~self.x_stall):
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m.d.sync += [
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m_rs1_addr.eq(x_rs1_addr),
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m_rs2_addr.eq(x_rs2_addr),
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m_rs1_rdata.eq(x_rs1_rdata),
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m_rs2_rdata.eq(x_rs2_rdata)
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]
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with m.If(~self.m_stall):
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m.d.sync += [
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self.rvfi.rs1_addr.eq(m_rs1_addr),
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self.rvfi.rs2_addr.eq(m_rs2_addr),
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self.rvfi.rs1_rdata.eq(m_rs1_rdata),
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self.rvfi.rs2_rdata.eq(m_rs2_rdata)
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]
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m.d.comb += [
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self.rvfi.rd_addr.eq(self.w_rd_addr),
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self.rvfi.rd_wdata.eq(self.w_rd_wdata)
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]
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# Program Counter
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m_pc_wdata = Signal.like(self.rvfi.pc_wdata)
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with m.If(self.m_exception):
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m.d.comb += m_pc_wdata.eq(self.mtvec_r_base << 2)
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with m.Elif(self.m_mret):
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m.d.comb += m_pc_wdata.eq(self.mepc_r_value)
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with m.Elif(self.m_branch_taken):
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m.d.comb += m_pc_wdata.eq(self.m_branch_target)
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with m.Else():
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m.d.comb += m_pc_wdata.eq(self.m_pc_rdata + 4)
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with m.If(~self.m_stall):
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m.d.sync += [
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self.rvfi.pc_rdata.eq(self.m_pc_rdata),
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self.rvfi.pc_wdata.eq(m_pc_wdata)
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]
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# Memory Access
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m_mem_addr = Signal.like(self.rvfi.mem_addr)
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m_mem_wmask = Signal.like(self.rvfi.mem_wmask)
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m_mem_rmask = Signal.like(self.rvfi.mem_rmask)
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m_mem_wdata = Signal.like(self.rvfi.mem_wdata)
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with m.If(~self.x_stall):
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m.d.sync += [
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m_mem_addr.eq(self.x_mem_addr),
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m_mem_wmask.eq(self.x_mem_wmask),
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m_mem_rmask.eq(self.x_mem_rmask),
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m_mem_wdata.eq(self.x_mem_wdata)
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]
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with m.If(~self.m_stall):
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m.d.sync += [
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self.rvfi.mem_addr.eq(m_mem_addr),
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self.rvfi.mem_wmask.eq(m_mem_wmask),
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self.rvfi.mem_rmask.eq(m_mem_rmask),
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self.rvfi.mem_wdata.eq(m_mem_wdata),
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self.rvfi.mem_rdata.eq(self.m_mem_rdata)
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]
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return m
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