riscv-formal-nmigen/rvfi/insns/insn_srli.py

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2020-08-17 11:50:53 +08:00
from .insn_rv32i_i_type_shift import *
2020-08-10 12:35:49 +08:00
"""
SRLI instruction
"""
class InsnSrli(InsnRV32IITypeShift):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b101)
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def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> self.insn_shamt, 0))
return m