58 lines
1.9 KiB
Python
58 lines
1.9 KiB
Python
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from nmigen import *
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from nmigen.asserts import *
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"""
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PC Forward Check
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"""
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class PcFwdCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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# Address validity and equality
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self.rvformal_addr_valid = rvformal_addr_valid
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self.rvformal_addr_eq = lambda a, b: (self.rvformal_addr_valid(a) == self.rvformal_addr_valid(b)) & ((~self.rvformal_addr_valid(a)) | (a == b))
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# Input ports
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self.reset = Signal(1)
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.reset,
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self.check,
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self.rvfi_valid,
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self.rvfi_order,
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self.rvfi_pc_rdata,
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self.rvfi_pc_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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expect_pc = Signal(self.RISCV_FORMAL_XLEN)
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expect_pc_valid = Signal(1, reset=0)
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pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
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with m.If(self.reset):
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m.d.sync += expect_pc_valid.eq(0)
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with m.Else():
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with m.If(self.check):
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m.d.comb += Assume(self.rvfi_valid)
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m.d.comb += Assume(insn_order == self.rvfi_order)
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with m.If(expect_pc_valid):
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m.d.comb += Assert(self.rvformal_addr_eq(expect_pc, pc_rdata))
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with m.Else():
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with m.If(self.rvfi_valid & (self.rvfi_order == insn_order - 1)):
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m.d.sync += expect_pc.eq(self.rvfi_pc_wdata)
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m.d.sync += expect_pc_valid.eq(1)
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return m
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