2020-08-06 14:13:00 +08:00
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# RISC-V Supported Instructions
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## Instructions
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| Instruction type | Instructions |
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2020-08-06 14:45:51 +08:00
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| --- | --- |
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2020-08-06 14:13:00 +08:00
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| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
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| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
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| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
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| S-type | SB, SD, SH, SW |
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| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
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| U-type | AUIPC, LUI |
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2020-08-06 16:44:54 +08:00
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| UJ-type | JAL |
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| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV |
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| CI-type (SP variation) | C\_ADDI16SP |
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| CI-type (ANDI variation) | C\_ANDI |
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| CI-type (LSP variation, 32 bit version) | C\_LWSP |
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| CI-type (LSP variation, 64 bit version) | C\_LDSP |
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| CI-type (LUI variation) | C\_LUI |
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| CI-type (SLI variation) | C\_SLLI |
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| CI-type (SRI variation) | C\_SRAI, C\_SRLI |
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| CIW-type | C\_ADDI4SPN |
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| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR |
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| CS-type (32 bit version) | C\_SW |
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| CS-type (64 bit version) | C\_SD |
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| CSS-type (32 bit version) | C\_SWSP |
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| CSS-type (64 bit version) | C\_SDSP |
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| CB-type | C\_BEQZ, C\_BNEZ |
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| CJ-type | C\_J, C\_JAL |
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| CL-type (32 bit version) | C\_LW |
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| CL-type (64 bit version) | C\_LD |
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2020-08-07 12:54:31 +08:00
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## Class Synopsis
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2020-08-06 14:13:00 +08:00
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2020-08-07 12:54:31 +08:00
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_Note: This section is under development and will be updated as more classes are implemented._
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- `Insn`: General RISC-V instruction
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2020-08-07 16:06:15 +08:00
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- `InsnRV32IRType`: RV32I R-Type Instruction
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- `InsnAdd`: ADD instruction
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- `InsnSub`: SUB instruction
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- `InsnSll`: SLL instruction
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- `InsnSlt`: SLT instruction
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- `InsnSltu`: SLTU instruction
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- `InsnXor`: XOR instruction
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- `InsnSrl`: SRL instruction
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- `InsnSra`: SRA instruction
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- `InsnOr`: OR instruction
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- `InsnAnd`: AND instruction
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2020-08-10 12:59:00 +08:00
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- `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation)
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- `InsnSlli`: SLLI instruction
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- `InsnSrli`: SRLI instruction
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- `InsnSrai`: SRAI instruction
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2020-08-10 14:14:40 +08:00
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- `InsnRV32IIType`: RV32I I-Type Instruction
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- `InsnJalr`: JALR instruction
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2020-08-06 14:13:00 +08:00
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## Parameters
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TODO
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