riscv-formal-nmigen/rvfi/cores/minerva/verify.py

import unittest
from .test.test_cache import *
from .test.test_instructions import *
from .test.test_units_divider import *
from .test.test_units_multiplier import *

print("Verifying L1 cache ...")
test = L1CacheTestCase()
test.test_direct_mapped()
test.test_2_ways()

print("Verifying RV32I instructions ...")
LuiTestCase().verify()

print("Testing multiplier and divider ...")
unittest.main()