linuswck 6cef418756 gateware: Add CSR Ctrl to PL's MMCM ... - Generate 45 Degree Phase Shifted DDR Clock - PLLE2_Base -> MMCM_ADV for ddr clock dynamic phase shift - Add mmcm_rst, ddr_clk_ps, mmcm_locked status to CSR - Generate dco2d rst signal from mmcm and connect to the related logic		2024-11-08 16:33:17 +08:00
..
fsbl-support	add fast-servo fsbl support	2024-02-20 09:48:40 +08:00
linien-gateware	gateware: Add CSR Ctrl to PL's MMCM	2024-11-08 16:33:17 +08:00
pyfastservo	dac: fix initialization order	2024-08-20 16:35:49 +08:00
fast-servo.dts	add spidev on device tree	2024-03-15 11:46:51 +08:00
fsbl.patch	add fast-servo fsbl support	2024-02-20 09:48:40 +08:00
linien-fast-servo-gateware.patch	add fast-servo linien gateware	2024-03-01 16:39:56 +08:00
linien-fast-servo-server.patch	add fast-servo linien gateware	2024-03-01 16:39:56 +08:00
linien-pyrp3-monitor.patch	use libmonitor compiled by gnumake	2024-05-22 15:32:23 +08:00
u-boot.patch	device tree source from u-boot and cleanup	2024-02-20 09:51:44 +08:00