Firmware for Sinara Fast-Servo based on Not-OS and Linien

linuswck 6cef418756 gateware: Add CSR Ctrl to PL's MMCM ... - Generate 45 Degree Phase Shifted DDR Clock - PLLE2_Base -> MMCM_ADV for ddr clock dynamic phase shift - Add mmcm_rst, ddr_clk_ps, mmcm_locked status to CSR - Generate dco2d rst signal from mmcm and connect to the related logic		2024-11-08 16:33:17 +08:00
fast-servo	gateware: Add CSR Ctrl to PL's MMCM	2024-11-08 16:33:17 +08:00
not-os-patches	add grep and vim	2024-10-31 19:06:59 +08:00
.gitignore	add __pycache__	2024-03-01 16:39:56 +08:00
flake.lock	flake: update dependencies	2024-08-19 22:03:51 +08:00
flake.nix	flake: update to nixpkgs 24.05	2024-07-02 14:23:54 +08:00