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Fix adc and dac initialization #55

Merged
sb10q merged 1 commits from fsagbuya/nix-servo:adc_dac into master 2024-06-11 13:59:38 +08:00
Conversation 6 Commits 1 Files Changed 2 +4 -4
2 changed files with 4 additions and 4 deletions
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6
fast-servo/pyfastservo/adc.py
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@ -54,7 +54,7 @@ def main_adc_config(test_pattern):
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE) spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000 spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0 spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True spi.cshigh = False
# spi.read0 = False # spi.read0 = False
spi_buffer = [0x00, 0x80] # reset spi_buffer = [0x00, 0x80] # reset
@ -121,7 +121,7 @@ def main_adc_test_mode(enable):
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE) spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000 spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0 spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True spi.cshigh = False
# spi.read0 = True # spi.read0 = True
reg_contents = ( reg_contents = (
@ -292,7 +292,7 @@ def adc_aux_read(port, type, pin):
spi.open(1, 3) # AUX ADC 1? spi.open(1, 3) # AUX ADC 1?
spi.max_speed_hz = 5000 spi.max_speed_hz = 5000
spi.mode = 0b00 spi.mode = 0b00
spi.cshigh = True spi.cshigh = False
read_buffer = spi.xfer2(write_buffer) read_buffer = spi.xfer2(write_buffer)
mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2 mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2

2
fast-servo/pyfastservo/dac.py
View File

@ -45,7 +45,7 @@ def main_dac_init():
spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE) spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
spi.max_speed_hz = 5000 spi.max_speed_hz = 5000
spi.mode = 0b00 # CPOL = 0 CPHA = 0 spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True spi.cshigh = False
spi_buffer = [0x00, 0x10] # software reset spi_buffer = [0x00, 0x10] # software reset
spi.xfer2(spi_buffer) spi.xfer2(spi_buffer)