Fix adc and dac initialization #55

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fsagbuya wants to merge 1 commits from fsagbuya/nix-servo:adc_dac into master
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Description

Fix the spi readback errors in adc.py and unrecognized device in dac.py, by configuring the following:

  • set spi.cshigh to False as per adc and dac datasheets.
  • introduce a delay to properly reset adc

See #49 log for comparison.

ADC init log:

Spi readback register 0x01: 0x20
Spi readback register 0x02: 0x15
Spi readback register 0x03: 0x81
Spi readback register 0x04: 0x1f
No bitslip required; Currernt frame = 0x0c
Tap delay: 0
Current frame: 0x0c
Tap delay: 1
Current frame: 0x0c
Tap delay: 2
Current frame: 0x0c
Tap delay: 3
Current frame: 0x0c
Tap delay: 4
Current frame: 0x0c
Tap delay: 5
Current frame: 0x0c
Tap delay: 6
Current frame: 0x0c
Tap delay: 7
Current frame: 0x0c
Tap delay: 8
Current frame: 0x0c
Tap delay: 9
Current frame: 0x0c
Tap delay: 10
Current frame: 0x0c
Tap delay: 11
Current frame: 0x0c
Tap delay: 12
Current frame: 0x0c
Tap delay: 13
Current frame: 0x0c
Tap delay: 14
Current frame: 0x0c
Tap delay: 15
Current frame: 0x0c
Tap delay: 16
Current frame: 0x0c
Tap delay: 17
Current frame: 0x0c
Tap delay: 18
Current frame: 0x0c
Tap delay: 19
Current frame: 0x0c
Tap delay: 20
Current frame: 0x0c
Tap delay: 21
Current frame: 0x0c
Tap delay: 22
Current frame: 0x0c
Tap delay: 23
Current frame: 0x0c
Tap delay: 24
Current frame: 0x0c
Tap delay: 25
Current frame: 0x0c
Tap delay: 26
Current frame: 0x0c
Tap delay: 27
Current frame: 0x0c
Tap delay: 28
Current frame: 0x0c
Tap delay: 29
Current frame: 0x0c
Tap delay: 30
Current frame: 0x0c
Tap delay: 31
Current frame: 0x0c
No edge detected; setting iDelay to: 11
ADC_CH0: 0x[65, 0, 0, 0]
Final ADC_CH0: 0x41aa
Final ADC_CH1: 0xf055
Spi readback register 0x02: 0x11
12

DAC init log:

=== Contents of spi buffer after DAC VERSION read back: ===
0x9F0A
0x8234
0x82B4
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
0x94D3
REG contents: 0b000
REG contents: 0b000

### Description Fix the `spi readback errors` in adc.py and `unrecognized device` in dac.py, by configuring the following: - set `spi.cshigh` to `False` as per [adc](https://www.analog.com/media/en/technical-documentation/data-sheets/219543f.pdf) and [dac ](https://www.analog.com/media/en/technical-documentation/data-sheets/ad9114_9115_9116_9117.pdf) datasheets. - introduce a delay to properly reset adc See #49 log for comparison. ADC init log: ``` Spi readback register 0x01: 0x20 Spi readback register 0x02: 0x15 Spi readback register 0x03: 0x81 Spi readback register 0x04: 0x1f No bitslip required; Currernt frame = 0x0c Tap delay: 0 Current frame: 0x0c Tap delay: 1 Current frame: 0x0c Tap delay: 2 Current frame: 0x0c Tap delay: 3 Current frame: 0x0c Tap delay: 4 Current frame: 0x0c Tap delay: 5 Current frame: 0x0c Tap delay: 6 Current frame: 0x0c Tap delay: 7 Current frame: 0x0c Tap delay: 8 Current frame: 0x0c Tap delay: 9 Current frame: 0x0c Tap delay: 10 Current frame: 0x0c Tap delay: 11 Current frame: 0x0c Tap delay: 12 Current frame: 0x0c Tap delay: 13 Current frame: 0x0c Tap delay: 14 Current frame: 0x0c Tap delay: 15 Current frame: 0x0c Tap delay: 16 Current frame: 0x0c Tap delay: 17 Current frame: 0x0c Tap delay: 18 Current frame: 0x0c Tap delay: 19 Current frame: 0x0c Tap delay: 20 Current frame: 0x0c Tap delay: 21 Current frame: 0x0c Tap delay: 22 Current frame: 0x0c Tap delay: 23 Current frame: 0x0c Tap delay: 24 Current frame: 0x0c Tap delay: 25 Current frame: 0x0c Tap delay: 26 Current frame: 0x0c Tap delay: 27 Current frame: 0x0c Tap delay: 28 Current frame: 0x0c Tap delay: 29 Current frame: 0x0c Tap delay: 30 Current frame: 0x0c Tap delay: 31 Current frame: 0x0c No edge detected; setting iDelay to: 11 ADC_CH0: 0x[65, 0, 0, 0] Final ADC_CH0: 0x41aa Final ADC_CH1: 0xf055 Spi readback register 0x02: 0x11 12 ``` DAC init log: ``` === Contents of spi buffer after DAC VERSION read back: === 0x9F0A 0x8234 0x82B4 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 0x94D3 REG contents: 0b000 REG contents: 0b000 ```
fsagbuya added 1 commit 2024-04-15 15:44:07 +08:00

Where is this coming from? Is the elhep code incorrect?

Where is this coming from? Is the elhep code incorrect?
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Where is this coming from? Is the elhep code incorrect?

This needs to be verify with the current elhep code, since the datasheet indicate this as default setup. Will inquire on it.

> Where is this coming from? Is the elhep code incorrect? This needs to be verify with the current elhep code, since the datasheet indicate this as default setup. Will inquire on it.

What datasheet?
Any answers from Jakub?

What datasheet? Any answers from Jakub?
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Reference: M-Labs/nix-servo#55
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