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Fix adc and dac initialization #55

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fsagbuya wants to merge 1 commits from fsagbuya/nix-servo:adc_dac into master
pull from: fsagbuya/nix-servo:adc_dac
merge into: M-Labs:master
Conversation 3 Commits 1 Files Changed 2
2 changed files with 6 additions and 4 deletions
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8
fast-servo/pyfastservo/adc.py
View File

@ -19,6 +19,7 @@
import mmap
import os
import time
import spidev
from common import (
@ -54,13 +55,14 @@ def main_adc_config(test_pattern):
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True
spi.cshigh = False
# spi.read0 = False
spi_buffer = [0x00, 0x80] # reset
rx_buffer = [0x00, 0x00]
spi.xfer2(spi_buffer)
time.sleep(0.1)
# REGISTER A1
spi_buffer = [0x01, 0x20] # set to Two's complement Data Format
@ -121,7 +123,7 @@ def main_adc_test_mode(enable):
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True
spi.cshigh = False
# spi.read0 = True
reg_contents = (
@ -292,7 +294,7 @@ def adc_aux_read(port, type, pin):
spi.open(1, 3) # AUX ADC 1?
spi.max_speed_hz = 5000
spi.mode = 0b00
spi.cshigh = True
spi.cshigh = False
read_buffer = spi.xfer2(write_buffer)
mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2

2
fast-servo/pyfastservo/dac.py
View File

@ -45,7 +45,7 @@ def main_dac_init():
spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
spi.max_speed_hz = 5000
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = True
spi.cshigh = False
spi_buffer = [0x00, 0x10] # software reset
spi.xfer2(spi_buffer)