 occheung
|
d47f9b4655
|
mqtt_mux: use nom
|
2020-09-21 17:31:34 +08:00 |
|
occheung
|
25f8363e54
|
dds: add RAM mode
|
2020-09-18 12:25:39 +08:00 |
|
occheung
|
412e6c0ea9
|
dds: allow single tone iterative setup
|
2020-09-16 14:23:01 +08:00 |
|
occheung
|
e1abf87351
|
dds: more clk ctrl; scpi: sys_clk ctrl
|
2020-09-16 12:05:45 +08:00 |
|
occheung
|
331d1ff86f
|
mqtt_to_scpi: strip away expected topic
|
2020-09-15 17:50:35 +08:00 |
|
occheung
|
b502b42c92
|
scpi: fix frequency control
|
2020-09-15 14:03:59 +08:00 |
|
occheung
|
4b52aa7099
|
mqtt: added mqtt to scpi conv
|
2020-09-15 12:17:42 +08:00 |
|
occheung
|
82867178f9
|
fix: reduce warning
|
2020-09-14 17:33:50 +08:00 |
|
occheung
|
43ccb86697
|
scpi: adopt rust standard on result/option handling
|
2020-09-14 15:36:03 +08:00 |
|
occheung
|
ecdb114679
|
src: replace hprint with logging
|
2020-09-10 14:35:47 +08:00 |
|
occheung
|
6616489a5e
|
scpi: refine clock src cmd
|
2020-09-07 17:52:37 +08:00 |
|
occheung
|
7665a23896
|
scpi: introduce master clock setup
|
2020-09-07 14:07:39 +08:00 |
|
occheung
|
56cb6eb3fd
|
scpi: redesign sw
|
2020-09-04 13:29:50 +08:00 |
|
occheung
|
37b7cc71b7
|
scpi: add switch ctrl command
|
2020-09-03 17:41:27 +08:00 |
|
occheung
|
13bf8b6080
|
nal-client: init
|
2020-09-01 14:50:49 +08:00 |
|
occheung
|
8dbf621679
|
scpi: implement tst
|
2020-08-31 17:43:15 +08:00 |
|
occheung
|
f60ec09b29
|
scpi: implement rst
|
2020-08-31 16:48:21 +08:00 |
|
occheung
|
d78f85721f
|
ethernet: minimal impl for urukul as scpi device
|
2020-08-31 13:32:08 +08:00 |
|
occheung
|
b0272a6fc2
|
urukul: add commented code, but with lifetime conflict
|
2020-08-31 12:32:39 +08:00 |
|
occheung
|
49594dfb3b
|
urukul: very bad constructor
|
2020-08-31 11:36:05 +08:00 |
|
occheung
|
4852fc54ea
|
cpld: detach from lib.rs
|
2020-08-31 09:31:56 +08:00 |
|
occheung
|
f92b2ba6f5
|
ethernet: add scpi to silent socket example
|
2020-08-28 15:48:13 +08:00 |
|
occheung
|
1d3ced0d16
|
dds: add clock control
|
2020-08-26 16:49:37 +08:00 |
|
occheung
|
38b1c7528c
|
dds: add register io
|
2020-08-26 13:18:50 +08:00 |
|
occheung
|
990fc075f1
|
cpld: add size_of
|
2020-08-26 11:04:39 +08:00 |
|
occheung
|
29abca72cd
|
cpld: auto invoke io update
|
2020-08-24 17:03:44 +08:00 |
|
occheung
|
dbea9aba30
|
attenuator: fix return data
|
2020-08-21 14:18:33 +08:00 |
|
occheung
|
8547610661
|
dds: add register io
|
2020-08-17 12:15:11 +08:00 |
|
occheung
|
495bf21575
|
bitmask_macro: separated from cfg_reg
|
2020-08-13 16:51:08 +08:00 |
|
occheung
|
0df7ff71cf
|
cfg_reg: add bitmask macro
|
2020-08-11 16:51:17 +08:00 |
|
occheung
|
a1a10d7afe
|
cfg_reg: init
|
2020-08-11 11:29:47 +08:00 |
|
occheung
|
00938bcb23
|
attenuator: init
|
2020-08-11 00:07:07 +08:00 |
|
occheung
|
2def3ed95d
|
rust: changed crate structure
|
2020-08-10 18:06:15 +08:00 |
|
occheung
|
429fbb7443
|
cpld: fixed unwanted mut
|
2020-08-10 17:22:46 +08:00 |
|
occheung
|
a406dea0c7
|
cpld: spi slave WIP
|
2020-08-10 17:04:40 +08:00 |