cpld: add release
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58e77ae671
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11
src/cpld.rs
11
src/cpld.rs
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@ -48,15 +48,20 @@ impl<SPI, CS0, CS1, CS2> CPLD<SPI, CS0, CS1, CS2> where
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match channel & (1 << 0) {
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match channel & (1 << 0) {
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0 => self.chip_select.0.set_low(),
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0 => self.chip_select.0.set_low(),
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_ => self.chip_select.0.set_high(),
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_ => self.chip_select.0.set_high(),
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};
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}.ok();
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match channel & (1 << 1) {
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match channel & (1 << 1) {
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0 => self.chip_select.1.set_low(),
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0 => self.chip_select.1.set_low(),
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_ => self.chip_select.1.set_high(),
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_ => self.chip_select.1.set_high(),
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};
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}.ok();
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match channel & (1 << 2) {
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match channel & (1 << 2) {
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0 => self.chip_select.2.set_low(),
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0 => self.chip_select.2.set_low(),
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_ => self.chip_select.2.set_high(),
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_ => self.chip_select.2.set_high(),
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};
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}.ok();
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}
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// Return the SPI and CS pins
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pub fn release(self) -> (SPI, (CS0, CS1, CS2)) {
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return (self.spi, self.chip_select);
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}
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}
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}
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}
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