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M-Labs
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artiq
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668997a451
artiq
/
artiq
/
gateware
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drtio
/
wrpll
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Spaqin
17efc28dbe
DRTIO: RTIO/SYS clock merge
2022-12-17 15:39:54 +08:00
..
__init__.py
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
core.py
DRTIO: RTIO/SYS clock merge
2022-12-17 15:39:54 +08:00
ddmtd.py
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
filters.py
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
2020-10-08 15:32:27 +08:00
si549.py
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
thls.py
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00