mirror of https://github.com/m-labs/artiq
619 lines
19 KiB
Python
619 lines
19 KiB
Python
import inspect
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import ast
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from copy import copy
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import operator
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from functools import reduce
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from collections import OrderedDict
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from migen import *
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from migen.genlib.fsm import *
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class Isn:
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def __init__(self, immediate=None, inputs=None, outputs=None):
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if inputs is None:
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inputs = []
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if outputs is None:
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outputs = []
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self.immediate = immediate
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self.inputs = inputs
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self.outputs = outputs
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def __repr__(self):
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r = "<"
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r += self.__class__.__name__
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if self.immediate is not None:
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r += " (" + str(self.immediate) + ")"
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for inp in self.inputs:
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r += " r" + str(inp)
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if self.outputs:
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r += " ->"
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for outp in self.outputs:
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r += " r" + str(outp)
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r += ">"
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return r
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class NopIsn(Isn):
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opcode = 0
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class AddIsn(Isn):
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opcode = 1
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class SubIsn(Isn):
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opcode = 2
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class MulShiftIsn(Isn):
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opcode = 3
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# opcode = 4: MulShift with alternate shift
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class MinIsn(Isn):
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opcode = 5
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class MaxIsn(Isn):
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opcode = 6
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class CopyIsn(Isn):
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opcode = 7
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class InputIsn(Isn):
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opcode = 8
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class OutputIsn(Isn):
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opcode = 9
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class EndIsn(Isn):
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opcode = 10
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class ASTCompiler:
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def __init__(self):
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self.program = []
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self.data = []
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self.next_ssa_reg = -1
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self.constants = dict()
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self.names = dict()
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self.globals = OrderedDict()
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def get_ssa_reg(self):
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r = self.next_ssa_reg
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self.next_ssa_reg -= 1
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return r
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def add_global(self, name):
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if name not in self.globals:
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r = len(self.data)
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self.data.append(0)
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self.names[name] = r
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self.globals[name] = r
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def input(self, name):
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target = self.get_ssa_reg()
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self.program.append(InputIsn(outputs=[target]))
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self.names[name] = target
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def emit(self, node):
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if isinstance(node, ast.BinOp):
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if isinstance(node.op, ast.RShift):
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if not isinstance(node.left, ast.BinOp) or not isinstance(node.left.op, ast.Mult):
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raise NotImplementedError
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if not isinstance(node.right, ast.Num):
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raise NotImplementedError
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left = self.emit(node.left.left)
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right = self.emit(node.left.right)
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cons = lambda **kwargs: MulShiftIsn(immediate=node.right.n, **kwargs)
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else:
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left = self.emit(node.left)
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right = self.emit(node.right)
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if isinstance(node.op, ast.Add):
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cons = AddIsn
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elif isinstance(node.op, ast.Sub):
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cons = SubIsn
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elif isinstance(node.op, ast.Mult):
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cons = lambda **kwargs: MulShiftIsn(immediate=0, **kwargs)
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else:
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raise NotImplementedError
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output = self.get_ssa_reg()
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self.program.append(cons(inputs=[left, right], outputs=[output]))
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return output
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elif isinstance(node, ast.Call):
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if not isinstance(node.func, ast.Name):
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raise NotImplementedError
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funcname = node.func.id
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if node.keywords:
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raise NotImplementedError
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inputs = [self.emit(x) for x in node.args]
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if funcname == "min":
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cons = MinIsn
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elif funcname == "max":
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cons = MaxIsn
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else:
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raise NotImplementedError
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output = self.get_ssa_reg()
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self.program.append(cons(inputs=inputs, outputs=[output]))
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return output
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elif isinstance(node, (ast.Num, ast.UnaryOp)):
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if isinstance(node, ast.UnaryOp):
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if not isinstance(node.operand, ast.Num):
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raise NotImplementedError
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if isinstance(node.op, ast.UAdd):
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transform = lambda x: x
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elif isinstance(node.op, ast.USub):
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transform = operator.neg
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elif isinstance(node.op, ast.Invert):
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transform = operator.invert
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else:
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raise NotImplementedError
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node = node.operand
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else:
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transform = lambda x: x
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n = transform(node.n)
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if n in self.constants:
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return self.constants[n]
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else:
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r = len(self.data)
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self.data.append(n)
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self.constants[n] = r
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return r
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elif isinstance(node, ast.Name):
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return self.names[node.id]
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elif isinstance(node, ast.Assign):
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output = self.emit(node.value)
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for target in node.targets:
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assert isinstance(target, ast.Name)
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self.names[target.id] = output
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elif isinstance(node, ast.Return):
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value = self.emit(node.value)
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self.program.append(OutputIsn(inputs=[value]))
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elif isinstance(node, ast.Global):
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pass
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else:
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raise NotImplementedError
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class Processor:
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def __init__(self, data_width=32, multiplier_stages=2):
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self.data_width = data_width
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self.multiplier_stages = multiplier_stages
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self.multiplier_shifts = []
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self.program_rom_size = None
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self.data_ram_size = None
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self.opcode_bits = 4
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self.reg_bits = None
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def get_instruction_latency(self, isn):
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return {
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AddIsn: 2,
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SubIsn: 2,
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MulShiftIsn: 1 + self.multiplier_stages,
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MinIsn: 2,
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MaxIsn: 2,
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CopyIsn: 1,
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InputIsn: 1
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}[isn.__class__]
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def encode_instruction(self, isn, exit):
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opcode = isn.opcode
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if isn.immediate is not None and not isinstance(isn, MulShiftIsn):
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r0 = isn.immediate
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if len(isn.inputs) >= 1:
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r1 = isn.inputs[0]
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else:
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r1 = 0
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else:
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if len(isn.inputs) >= 1:
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r0 = isn.inputs[0]
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else:
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r0 = 0
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if len(isn.inputs) >= 2:
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r1 = isn.inputs[1]
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else:
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r1 = 0
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r = 0
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for value, bits in ((exit, self.reg_bits), (r1, self.reg_bits), (r0, self.reg_bits), (opcode, self.opcode_bits)):
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r <<= bits
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r |= value
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return r
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def instruction_bits(self):
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return 3*self.reg_bits + self.opcode_bits
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def implement(self, program, data):
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return ProcessorImpl(self, program, data)
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class Scheduler:
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def __init__(self, processor, reserved_data, program):
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self.processor = processor
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self.reserved_data = reserved_data
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self.used_registers = set(range(self.reserved_data))
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self.exits = dict()
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self.program = program
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self.remaining = copy(program)
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self.output = []
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def allocate_register(self):
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r = min(set(range(max(self.used_registers) + 2)) - self.used_registers)
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self.used_registers.add(r)
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return r
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def free_register(self, r):
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assert r >= self.reserved_data
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self.used_registers.discard(r)
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def find_inputs(self, cycle, isn):
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mapped_inputs = []
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for inp in isn.inputs:
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if inp >= 0:
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mapped_inputs.append(inp)
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else:
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found = False
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for i in range(cycle):
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if i in self.exits:
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r, rm = self.exits[i]
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if r == inp:
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mapped_inputs.append(rm)
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found = True
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break
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if not found:
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return None
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return mapped_inputs
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def schedule_one(self, isn):
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cycle = len(self.output)
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mapped_inputs = self.find_inputs(cycle, isn)
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if mapped_inputs is None:
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return False
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if isn.outputs:
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# check that exit slot is free
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latency = self.processor.get_instruction_latency(isn)
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exit = cycle + latency
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if exit in self.exits:
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return False
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# avoid RAW hazard with global writeback
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for output in isn.outputs:
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if output >= 0:
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for risn in self.remaining:
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for inp in risn.inputs:
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if inp == output:
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return False
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# Instruction can be scheduled
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self.remaining.remove(isn)
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for inp, minp in zip(isn.inputs, mapped_inputs):
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can_free = inp < 0 and all(inp != rinp for risn in self.remaining for rinp in risn.inputs)
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if can_free:
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self.free_register(minp)
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if isn.outputs:
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assert len(isn.outputs) == 1
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if isn.outputs[0] < 0:
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output = self.allocate_register()
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else:
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output = isn.outputs[0]
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self.exits[exit] = (isn.outputs[0], output)
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self.output.append(isn.__class__(immediate=isn.immediate, inputs=mapped_inputs))
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return True
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def schedule(self):
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while self.remaining:
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success = False
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for isn in self.remaining:
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if self.schedule_one(isn):
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success = True
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break
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if not success:
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self.output.append(NopIsn())
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self.output += [NopIsn()]*(max(self.exits.keys()) - len(self.output) + 1)
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return self.output
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class CompiledProgram:
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def __init__(self, processor, program, exits, data, glbs):
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self.processor = processor
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self.program = program
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self.exits = exits
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self.data = data
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self.globals = glbs
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def pretty_print(self):
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for cycle, isn in enumerate(self.program):
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l = "{:4d} {:15}".format(cycle, str(isn))
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if cycle in self.exits:
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l += " -> r{}".format(self.exits[cycle])
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print(l)
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def dimension_processor(self):
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self.processor.program_rom_size = len(self.program)
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self.processor.data_ram_size = len(self.data)
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self.processor.reg_bits = (self.processor.data_ram_size - 1).bit_length()
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for isn in self.program:
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if isinstance(isn, MulShiftIsn) and isn.immediate not in self.processor.multiplier_shifts:
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self.processor.multiplier_shifts.append(isn.immediate)
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def encode(self):
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r = []
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for i, isn in enumerate(self.program):
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exit = self.exits.get(i, 0)
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r.append(self.processor.encode_instruction(isn, exit))
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return r
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def compile(processor, function):
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node = ast.parse(inspect.getsource(function))
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assert isinstance(node, ast.Module)
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assert len(node.body) == 1
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node = node.body[0]
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assert isinstance(node, ast.FunctionDef)
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assert len(node.args.args) == 1
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arg = node.args.args[0].arg
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body = node.body
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astcompiler = ASTCompiler()
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for node in body:
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if isinstance(node, ast.Global):
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for name in node.names:
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astcompiler.add_global(name)
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arg_r = astcompiler.input(arg)
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for node in body:
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astcompiler.emit(node)
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if isinstance(node, ast.Return):
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break
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for glbl, location in astcompiler.globals.items():
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new_location = astcompiler.names[glbl]
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if new_location != location:
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astcompiler.program.append(CopyIsn(inputs=[new_location], outputs=[location]))
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scheduler = Scheduler(processor, len(astcompiler.data), astcompiler.program)
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scheduler.schedule()
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program = copy(scheduler.output)
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program.append(EndIsn())
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max_reg = max(max(max(isn.inputs + [0]) for isn in program), max(v[1] for k, v in scheduler.exits.items()))
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return CompiledProgram(
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processor=processor,
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program=program,
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exits={k: v[1] for k, v in scheduler.exits.items()},
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data=astcompiler.data + [0]*(max_reg - len(astcompiler.data) + 1),
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glbs=astcompiler.globals)
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class BaseUnit(Module):
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def __init__(self, data_width):
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self.stb_i = Signal()
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self.i0 = Signal((data_width, True))
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self.i1 = Signal((data_width, True))
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self.stb_o = Signal()
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self.o = Signal((data_width, True))
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class NopUnit(BaseUnit):
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pass
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class OpUnit(BaseUnit):
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def __init__(self, op, data_width, stages, op_data_width=None):
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BaseUnit.__init__(self, data_width)
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# work around Migen's mishandling of Verilog's cretinous operator width rules
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if op_data_width is None:
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op_data_width = data_width
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if stages > 1:
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# Vivado backward retiming for DSP does not work correctly if DSP inputs
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# are not registered.
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i0 = Signal.like(self.i0)
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i1 = Signal.like(self.i1)
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stb_i = Signal()
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self.sync += [
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i0.eq(self.i0),
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i1.eq(self.i1),
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stb_i.eq(self.stb_i)
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]
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output_stages = stages - 1
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else:
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i0, i1, stb_i = self.i0, self.i1, self.stb_i
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output_stages = stages
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o = Signal((op_data_width, True))
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self.comb += o.eq(op(i0, i1))
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stb_o = stb_i
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for i in range(output_stages):
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n_o = Signal((data_width, True))
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if stages > 1:
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n_o.attr.add(("retiming_backward", 1))
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n_stb_o = Signal()
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self.sync += [
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n_o.eq(o),
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n_stb_o.eq(stb_o)
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]
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o = n_o
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stb_o = n_stb_o
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self.comb += [
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self.o.eq(o),
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self.stb_o.eq(stb_o)
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]
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class SelectUnit(BaseUnit):
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def __init__(self, op, data_width):
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BaseUnit.__init__(self, data_width)
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self.sync += [
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self.stb_o.eq(self.stb_i),
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If(op(self.i0, self.i1),
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self.o.eq(self.i0)
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).Else(
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self.o.eq(self.i1)
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)
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]
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class CopyUnit(BaseUnit):
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def __init__(self, data_width):
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BaseUnit.__init__(self, data_width)
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self.comb += [
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self.stb_o.eq(self.stb_i),
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self.o.eq(self.i0)
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]
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class InputUnit(BaseUnit):
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def __init__(self, data_width, input_stb, input):
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BaseUnit.__init__(self, data_width)
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self.buffer = Signal(data_width)
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self.comb += [
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self.stb_o.eq(self.stb_i),
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self.o.eq(self.buffer)
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]
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class OutputUnit(BaseUnit):
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def __init__(self, data_width, output_stb, output):
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BaseUnit.__init__(self, data_width)
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self.sync += [
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output_stb.eq(self.stb_i),
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output.eq(self.i0)
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]
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class ProcessorImpl(Module):
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def __init__(self, pd, program, data):
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self.input_stb = Signal()
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self.input = Signal((pd.data_width, True))
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self.output_stb = Signal()
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self.output = Signal((pd.data_width, True))
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self.busy = Signal()
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# # #
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program_mem = Memory(pd.instruction_bits(), pd.program_rom_size, init=program)
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data_mem0 = Memory(pd.data_width, pd.data_ram_size, init=data)
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data_mem1 = Memory(pd.data_width, pd.data_ram_size, init=data)
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self.specials += program_mem, data_mem0, data_mem1
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pc = Signal(pd.instruction_bits())
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pc_next = Signal.like(pc)
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pc_en = Signal()
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self.sync += pc.eq(pc_next)
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self.comb += [
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If(pc_en,
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pc_next.eq(pc + 1)
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).Else(
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pc_next.eq(0)
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)
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]
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program_mem_port = program_mem.get_port()
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self.specials += program_mem_port
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self.comb += program_mem_port.adr.eq(pc_next)
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s = 0
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opcode = Signal(pd.opcode_bits)
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self.comb += opcode.eq(program_mem_port.dat_r[s:s+pd.opcode_bits])
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s += pd.opcode_bits
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r0 = Signal(pd.reg_bits)
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self.comb += r0.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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s += pd.reg_bits
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r1 = Signal(pd.reg_bits)
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self.comb += r1.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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s += pd.reg_bits
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exit = Signal(pd.reg_bits)
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self.comb += exit.eq(program_mem_port.dat_r[s:s+pd.reg_bits])
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data_read_port0 = data_mem0.get_port()
|
|
data_read_port1 = data_mem1.get_port()
|
|
self.specials += data_read_port0, data_read_port1
|
|
self.comb += [
|
|
data_read_port0.adr.eq(r0),
|
|
data_read_port1.adr.eq(r1)
|
|
]
|
|
|
|
data_write_port = data_mem0.get_port(write_capable=True)
|
|
data_write_port_dup = data_mem1.get_port(write_capable=True)
|
|
self.specials += data_write_port, data_write_port_dup
|
|
self.comb += [
|
|
data_write_port_dup.we.eq(data_write_port.we),
|
|
data_write_port_dup.adr.eq(data_write_port.adr),
|
|
data_write_port_dup.dat_w.eq(data_write_port.dat_w),
|
|
data_write_port.adr.eq(exit)
|
|
]
|
|
|
|
nop = NopUnit(pd.data_width)
|
|
adder = OpUnit(operator.add, pd.data_width, 1)
|
|
subtractor = OpUnit(operator.sub, pd.data_width, 1)
|
|
if pd.multiplier_shifts:
|
|
if len(pd.multiplier_shifts) != 1:
|
|
raise NotImplementedError
|
|
multiplier = OpUnit(lambda a, b: a * b >> pd.multiplier_shifts[0],
|
|
pd.data_width, pd.multiplier_stages, op_data_width=2*pd.data_width)
|
|
else:
|
|
multiplier = NopUnit(pd.data_width)
|
|
minu = SelectUnit(operator.lt, pd.data_width)
|
|
maxu = SelectUnit(operator.gt, pd.data_width)
|
|
copier = CopyUnit(pd.data_width)
|
|
inu = InputUnit(pd.data_width, self.input_stb, self.input)
|
|
outu = OutputUnit(pd.data_width, self.output_stb, self.output)
|
|
units = [nop, adder, subtractor, multiplier, minu, maxu, copier, inu, outu]
|
|
self.submodules += units
|
|
|
|
for unit in units:
|
|
self.sync += unit.stb_i.eq(0)
|
|
self.comb += [
|
|
unit.i0.eq(data_read_port0.dat_r),
|
|
unit.i1.eq(data_read_port1.dat_r),
|
|
If(unit.stb_o,
|
|
data_write_port.we.eq(1),
|
|
data_write_port.dat_w.eq(unit.o)
|
|
)
|
|
]
|
|
|
|
decode_table = [
|
|
(NopIsn.opcode, nop),
|
|
(AddIsn.opcode, adder),
|
|
(SubIsn.opcode, subtractor),
|
|
(MulShiftIsn.opcode, multiplier),
|
|
(MulShiftIsn.opcode + 1, multiplier),
|
|
(MinIsn.opcode, minu),
|
|
(MaxIsn.opcode, maxu),
|
|
(CopyIsn.opcode, copier),
|
|
(InputIsn.opcode, inu),
|
|
(OutputIsn.opcode, outu)
|
|
]
|
|
for allocated_opcode, unit in decode_table:
|
|
self.sync += If(pc_en & (opcode == allocated_opcode), unit.stb_i.eq(1))
|
|
|
|
fsm = FSM()
|
|
self.submodules += fsm
|
|
fsm.act("IDLE",
|
|
pc_en.eq(0),
|
|
NextValue(inu.buffer, self.input),
|
|
If(self.input_stb, NextState("PROCESSING"))
|
|
)
|
|
fsm.act("PROCESSING",
|
|
self.busy.eq(1),
|
|
pc_en.eq(1),
|
|
If(opcode == EndIsn.opcode,
|
|
pc_en.eq(0),
|
|
NextState("IDLE")
|
|
)
|
|
)
|
|
|
|
|
|
def make(function, **kwargs):
|
|
proc = Processor(**kwargs)
|
|
cp = compile(proc, function)
|
|
cp.dimension_processor()
|
|
return proc.implement(cp.encode(), cp.data)
|