artiq/artiq
whitequark 51e966edf2 Commit missing parts of 0b69e488. 2015-12-31 21:09:24 +08:00
..
applets applets: add XY/histogram plot demo 2015-12-28 16:48:31 +08:00
compiler transforms.llvm_ir_generator: compare exn typeinfo using strcmp. 2015-12-31 19:53:28 +08:00
coredevice coredevice.comm_generic: handle RPC default args correctly. 2015-12-29 02:54:34 +08:00
devices devices/thorlabs_tcube: minor cleanup 2015-11-25 21:43:22 +08:00
frontend frontend: bind v4 and v6 localhost addresses by default, support multiple bind 2015-12-27 18:03:13 +08:00
gateware targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance 2015-12-29 17:00:57 +08:00
gui gui/experiments: fix Qt compatibility issue with QHeaderView.setResizeMode 2015-12-13 19:32:17 +08:00
language language/environment: disable processors by default 2015-12-22 11:45:34 +08:00
master language/environment: disable processors by default 2015-12-22 11:45:34 +08:00
protocols remove workaround_asyncio263 2015-12-20 23:26:48 +08:00
runtime Commit missing parts of 0b69e488. 2015-12-31 21:09:24 +08:00
sim sim/devices/core: adapt to _ARTIQEmbeddedInfo 2015-12-27 11:56:01 +08:00
test test/coredevice/primes: keep output list entirely on the host 2015-12-31 09:49:37 +08:00
wavesynth copyright: claim contributions 2015-09-06 16:08:57 -06:00
__init__.py use versioneer 2015-11-09 11:33:38 +08:00
_version.py update versioneer 2015-11-09 12:19:01 +08:00
tools.py frontend: bind v4 and v6 localhost addresses by default, support multiple bind 2015-12-27 18:03:13 +08:00