Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) ... * gets another clock divider out of the way * gets one cycle within range of the HMC7043 analog delay alone * SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme		2019-01-25 13:47:04 +08:00
..
__init__.py	package everything to rebuild core device binaries	2015-11-09 10:47:14 +08:00
kasli.py	kasli: adapt Master target to new hardware	2019-01-24 18:27:15 +08:00
kc705.py	Merge branch 'master' into new	2018-11-19 11:54:50 +08:00
sayma_amc.py	sayma: 2.4GHz DAC clocking (4X interpolation)	2019-01-25 13:47:04 +08:00
sayma_rtm_drtio.py	add Sayma RTM DRTIO target	2019-01-07 00:13:47 +08:00
sayma_rtm.py	sayma_rtm: add hmc7043_gpo monitoring	2018-07-11 19:04:29 +08:00