mirror of https://github.com/m-labs/artiq.git
737 lines
30 KiB
Python
Executable File
737 lines
30 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os
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import warnings
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from migen import *
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from misoc.targets.sayma_amc import BaseSoC, MiniSoC
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import eem
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from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import serwb, remote_csr
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += self.sawgs
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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assert len(Cat(ch.o)) == len(conv)
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self.sync.jesd += conv.eq(Cat(ch.o))
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class AD9154NoSAWG(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.sawgs = []
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ramp = Signal(4)
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self.sync.rtio += ramp.eq(ramp + 1)
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samples = [[Signal(16) for i in range(4)] for j in range(4)]
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self.comb += [
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a.eq(Cat(b)) for a, b in zip(
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self.jesd.core.sink.flatten(), samples)
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]
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# ch0: 16-step ramp with big carry toggles
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for i in range(4):
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self.comb += [
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samples[0][i][-4:].eq(ramp),
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samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800)
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]
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# ch1: 50 MHz
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from math import pi, cos
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data = [int(round(cos(i/12*2*pi)*((1 << 15) - 1)))
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for i in range(12)]
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k = Signal(2)
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self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1))
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self.comb += [
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Case(k, {
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i: [samples[1][j].eq(data[i*4 + j]) for j in range(4)]
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for i in range(3)
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})
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]
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# ch2: ch0, ch3: ch1
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self.comb += [
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Cat(samples[2]).eq(Cat(samples[0])),
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Cat(samples[3]).eq(Cat(samples[1]))
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]
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class RTMCommon:
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def __init__(self):
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platform = self.platform
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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# RTM bitstream upload
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slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
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self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
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slave_fpga_cfg.cclk,
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slave_fpga_cfg.din,
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slave_fpga_cfg.done,
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slave_fpga_cfg.init_b,
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slave_fpga_cfg.program_b,
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])
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self.csr_devices.append("slave_fpga_cfg")
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self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master")
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave")
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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class Standalone(MiniSoC, AMPSoC, RTMCommon):
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"""
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Local DAC/SAWG channels only.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_SAYMA_REF"] = None
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("si5324_clkout", 0)
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self.specials += Instance(
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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# RTIO
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# To work around Ultrascale issues (https://www.xilinx.com/support/answers/67885.html),
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# we generate the multiplied RTIO clock using the DRTIO GTH transceiver.
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# Since there is no DRTIO here and therefoere no multiplied clock, we use ttl_simple.
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.clock_domains.cd_rtio = ClockDomain()
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self.comb += [
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self.cd_rtio.clk.eq(ClockSignal("jesd")),
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self.cd_rtio.rst.eq(ResetSignal("jesd"))
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]
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self.submodules.rtio_tsc = rtio.TSC("async")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"""
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DRTIO master with local DAC/SAWG channels.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"drtioaux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_SAYMA_REF"] = None
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("si5324_clkout", 0)
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self.specials += Instance(
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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self.csr_devices.append("ad9154_crg")
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(3):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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platform.add_false_path_constraints(
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
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self.drtio_transceiver.cd_rtio.clk)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + drtio_cri,
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
|
|
# See:
|
|
# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
|
|
platform.add_platform_command(
|
|
"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]"
|
|
" -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
|
|
|
|
|
|
class Master(MiniSoC, AMPSoC):
|
|
"""
|
|
DRTIO master with 2 SFP ports plus 8 lanes on RTM.
|
|
Use passive RTM adapter to connect to satellites.
|
|
Due to GTH clock routing restrictions, it is not possible
|
|
to use more RTM lanes without additional hardware.
|
|
"""
|
|
mem_map = {
|
|
"cri_con": 0x10000000,
|
|
"rtio": 0x11000000,
|
|
"rtio_dma": 0x12000000,
|
|
"drtioaux": 0x14000000,
|
|
"mailbox": 0x70000000
|
|
}
|
|
mem_map.update(MiniSoC.mem_map)
|
|
|
|
def __init__(self, **kwargs):
|
|
MiniSoC.__init__(self,
|
|
cpu_type="or1k",
|
|
sdram_controller_type="minicon",
|
|
l2_size=128*1024,
|
|
ethmac_nrxslots=4,
|
|
ethmac_ntxslots=4,
|
|
**kwargs)
|
|
AMPSoC.__init__(self)
|
|
add_identifier(self)
|
|
|
|
platform = self.platform
|
|
rtio_clk_freq = 150e6
|
|
|
|
# forward RTM UART to second FTDI UART channel
|
|
serial_1 = platform.request("serial", 1)
|
|
serial_rtm = platform.request("serial_rtm")
|
|
self.comb += [
|
|
serial_1.tx.eq(serial_rtm.rx),
|
|
serial_rtm.tx.eq(serial_1.rx)
|
|
]
|
|
|
|
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
|
self.csr_devices.append("si5324_rst_n")
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
|
|
self.comb += [
|
|
platform.request("sfp_tx_disable", i).eq(0)
|
|
for i in range(2)
|
|
]
|
|
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
|
|
clock_pads=platform.request("si5324_clkout", 0),
|
|
data_pads=[platform.request("sfp", i) for i in range(2)] +
|
|
[platform.request("rtm_gth", i) for i in range(8)],
|
|
sys_clk_freq=self.clk_freq,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
self.csr_devices.append("drtio_transceiver")
|
|
|
|
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
|
|
|
drtio_csr_group = []
|
|
drtioaux_csr_group = []
|
|
drtioaux_memory_group = []
|
|
drtio_cri = []
|
|
for i in range(10):
|
|
core_name = "drtio" + str(i)
|
|
coreaux_name = "drtioaux" + str(i)
|
|
memory_name = "drtioaux" + str(i) + "_mem"
|
|
drtio_csr_group.append(core_name)
|
|
drtioaux_csr_group.append(coreaux_name)
|
|
drtioaux_memory_group.append(memory_name)
|
|
|
|
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
|
|
|
core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
|
setattr(self.submodules, core_name, core)
|
|
drtio_cri.append(core.cri)
|
|
self.csr_devices.append(core_name)
|
|
|
|
coreaux = cdr(DRTIOAuxController(core.link_layer))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
|
self.add_wb_slave(memory_address, 0x800,
|
|
coreaux.bus)
|
|
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtio", drtio_csr_group)
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
gth0 = self.drtio_transceiver.gths[0]
|
|
platform.add_period_constraint(gth0.txoutclk, rtio_clk_period/2)
|
|
platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gth0.txoutclk, gth0.rxoutclk)
|
|
for gth in self.drtio_transceiver.gths[1:]:
|
|
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk)
|
|
|
|
self.rtio_channels = rtio_channels = []
|
|
for i in range(4):
|
|
phy = ttl_simple.Output(platform.request("user_led", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
sma_io = platform.request("sma_io", 0)
|
|
self.comb += sma_io.direction.eq(1)
|
|
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
sma_io = platform.request("sma_io", 1)
|
|
self.comb += sma_io.direction.eq(0)
|
|
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
platform.add_extension(fmcdio_vhdci_eem.io)
|
|
platform.add_connectors(fmcdio_vhdci_eem.connectors)
|
|
fmcdio_dirctl = platform.request("fmcdio_dirctl")
|
|
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
|
|
phy = ttl_simple.Output(s)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
|
|
iostandard="LVDS")
|
|
eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
|
|
iostandard="LVDS")
|
|
eem.Zotino.add_std(self, 3, ttl_simple.Output,
|
|
iostandard="LVDS")
|
|
workaround_us_lvds_tristate(platform)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
|
|
self.csr_devices.append("rtio_core")
|
|
|
|
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
|
|
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
|
rtio.DMA(self.get_native_sdram_if()))
|
|
self.register_kernel_cpu_csrdevice("rtio")
|
|
self.register_kernel_cpu_csrdevice("rtio_dma")
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.rtio.cri, self.rtio_dma.cri],
|
|
[self.rtio_core.cri] + drtio_cri,
|
|
enable_routing=True)
|
|
self.register_kernel_cpu_csrdevice("cri_con")
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
|
|
class Satellite(BaseSoC, RTMCommon):
|
|
"""
|
|
DRTIO satellite with local DAC/SAWG channels.
|
|
Use SFP0 to connect to master (Kasli/Sayma).
|
|
"""
|
|
mem_map = {
|
|
"serwb": 0x13000000,
|
|
"drtioaux": 0x14000000,
|
|
}
|
|
mem_map.update(BaseSoC.mem_map)
|
|
|
|
def __init__(self, with_sawg, **kwargs):
|
|
BaseSoC.__init__(self,
|
|
cpu_type="or1k",
|
|
sdram_controller_type="minicon",
|
|
l2_size=128*1024,
|
|
**kwargs)
|
|
RTMCommon.__init__(self)
|
|
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
|
|
self.config["HMC830_REF"] = "150"
|
|
|
|
platform = self.platform
|
|
rtio_clk_freq = 150e6
|
|
|
|
rtio_channels = []
|
|
for i in range(4):
|
|
phy = ttl_simple.Output(platform.request("user_led", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
sma_io = platform.request("sma_io", 0)
|
|
self.comb += sma_io.direction.eq(1)
|
|
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
sma_io = platform.request("sma_io", 1)
|
|
self.comb += sma_io.direction.eq(0)
|
|
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
|
|
platform, use_rtio_clock=True)
|
|
if with_sawg:
|
|
cls = AD9154
|
|
else:
|
|
cls = AD9154NoSAWG
|
|
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
|
|
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
|
|
self.csr_devices.append("ad9154_crg")
|
|
self.csr_devices.append("ad9154_0")
|
|
self.csr_devices.append("ad9154_1")
|
|
self.config["HAS_AD9154"] = None
|
|
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
|
|
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.extend(rtio.Channel.from_phy(phy)
|
|
for sawg in self.ad9154_0.sawgs +
|
|
self.ad9154_1.sawgs
|
|
for phy in sawg.phys)
|
|
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
|
|
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
|
|
clock_pads=platform.request("si5324_clkout"),
|
|
data_pads=[platform.request("sfp", 0)],
|
|
sys_clk_freq=self.clk_freq,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
self.csr_devices.append("drtio_transceiver")
|
|
|
|
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
|
|
|
|
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
|
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
|
|
self.submodules.drtiosat = rx0(DRTIOSatellite(
|
|
self.rtio_tsc, self.drtio_transceiver.channels[0],
|
|
self.rx_synchronizer))
|
|
self.csr_devices.append("drtiosat")
|
|
self.submodules.drtioaux0 = rx0(DRTIOAuxController(
|
|
self.drtiosat.link_layer))
|
|
self.csr_devices.append("drtioaux0")
|
|
self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
|
|
self.drtioaux0.bus)
|
|
self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.add_csr_group("drtioaux", ["drtioaux0"])
|
|
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
|
self.comb += [
|
|
self.drtiosat.cri.connect(self.local_io.cri),
|
|
self.drtiosat.async_errors.eq(self.local_io.async_errors),
|
|
]
|
|
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("si5324_clkin"),
|
|
rx_synchronizer=self.rx_synchronizer)
|
|
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
|
|
mmcm_ps=self.siphaser.mmcm_ps_output)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
|
self.csr_devices.append("siphaser")
|
|
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
|
self.csr_devices.append("si5324_rst_n")
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
gth = self.drtio_transceiver.gths[0]
|
|
platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
|
|
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gth.txoutclk, gth.rxoutclk)
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="Sayma AMC gateware and firmware builder")
|
|
builder_args(parser)
|
|
soc_sdram_args(parser)
|
|
parser.set_defaults(output_dir="artiq_sayma")
|
|
parser.add_argument("-V", "--variant", default="standalone",
|
|
help="variant: "
|
|
"standalone/masterdac/master/satellite "
|
|
"(default: %(default)s)")
|
|
parser.add_argument("--rtm-csr-csv",
|
|
default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
|
|
help="CSV file listing remote CSRs on RTM (default: %(default)s)")
|
|
parser.add_argument("--without-sawg",
|
|
default=False, action="store_true",
|
|
help="Remove SAWG RTIO channels feeding the JESD links (speeds up "
|
|
"compilation time). Replaces them with fixed pattern generators.")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
if variant == "standalone":
|
|
cls = Standalone
|
|
elif variant == "masterdac":
|
|
cls = MasterDAC
|
|
elif variant == "master":
|
|
cls = lambda with_sawg, **kwargs: Master(**kwargs)
|
|
elif variant == "satellite":
|
|
cls = Satellite
|
|
else:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
|
|
|
|
if variant != "master":
|
|
remote_csr_regions = remote_csr.get_remote_csr_regions(
|
|
soc.mem_map["serwb"] | soc.shadow_base,
|
|
args.rtm_csr_csv)
|
|
for name, origin, busword, csrs in remote_csr_regions:
|
|
soc.add_csr_region(name, origin, busword, csrs)
|
|
# Configuration for RTM peripherals. Keep in sync with sayma_rtm.py!
|
|
soc.config["HAS_HMC830_7043"] = None
|
|
soc.config["CONVERTER_SPI_HMC830_CS"] = 0
|
|
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
|
|
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
|
|
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|