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6de650a701
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doc/manual: minor fixes
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2014-12-02 19:23:15 +08:00 |
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2a843ea436
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language: replace AutoContext 'parameter' string with abstract attributes
This allows specifying default values for parameters, and other data.
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2014-12-02 17:19:05 +08:00 |
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83d3b97b23
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coredevice/comm_serial: give up on garbage received after baudrate change
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2014-12-02 16:04:41 +08:00 |
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cad5933709
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transforms/inline: do not writeback bool
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2014-12-02 15:53:41 +08:00 |
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649fedd656
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coredevice/core: fix recover_underflow
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2014-12-02 15:31:09 +08:00 |
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fc690ead75
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runtime: support clock switching
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2014-12-02 14:06:32 +08:00 |
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94218f785e
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comm_serial: cleanup
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2014-12-02 11:09:02 +08:00 |
|
Yann Sionneau
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20adb57140
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comm_serial: allow to use dynamic baudrate
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2014-12-02 10:42:14 +08:00 |
|
Yann Sionneau
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3ff3afe696
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manual: use theme options which looks like m-labs web site
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2014-12-02 10:32:27 +08:00 |
|
Yann Sionneau
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0c20445413
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lda: allow to simulate without needing hidapi
This also fixes some old style string formating
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2014-12-01 19:39:13 +08:00 |
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c591f1a74d
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targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
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2014-12-01 18:53:29 +08:00 |
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57d633f48e
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rtio: remove unnecessary attributes
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2014-12-01 17:47:24 +08:00 |
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cd587e4f12
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rtio: do housekeeping in gateware
|
2014-12-01 17:32:36 +08:00 |
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99d530e498
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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
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2014-12-01 17:31:35 +08:00 |
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3a27f49bff
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frontend/runelf: use new Comm
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2014-12-01 15:24:38 +08:00 |
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2146e58d20
|
frontend: rename files to avoid conflicts
|
2014-12-01 15:20:35 +08:00 |
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50e0bf3280
|
rtio: optimize flag handling
|
2014-12-01 14:29:50 +08:00 |
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572eecc57b
|
rtio: stricter upper bound on guard time to avoid race condition
|
2014-12-01 14:27:03 +08:00 |
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d50dbc0e73
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coredevice/runtime_exceptions: update RTIO exception behaviour doc
|
2014-12-01 13:57:25 +08:00 |
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7166ca82d1
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targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
|
2014-11-30 22:31:55 +08:00 |
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1f6441948d
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more TTL channels and larger input FIFOs on Papilio Pro
|
2014-11-30 15:50:57 +08:00 |
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e5286c57ab
|
rtio: fix input FIFO depth config
|
2014-11-30 12:12:35 +08:00 |
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bf745e53c9
|
rtio: register FIFO output to improve timing
|
2014-11-30 10:51:12 +08:00 |
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dda4002ae1
|
rtio/phy: fix input synchronization
|
2014-11-30 10:50:48 +08:00 |
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c78c5a2b4f
|
rtio: fix guard cycle computation
|
2014-11-30 01:00:52 +08:00 |
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39c4b5416f
|
targets/ARTIQMiniSoC: 125MHz RTIO clocking
|
2014-11-30 01:00:27 +08:00 |
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9aafe89518
|
rtio: use Record
|
2014-11-30 00:59:39 +08:00 |
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901073acf3
|
asynchronous RTIO
|
2014-11-30 00:13:54 +08:00 |
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9c41f98d70
|
lda_controller: fix memory leak
|
2014-11-29 11:19:03 +08:00 |
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26180e7905
|
manual/drivers_reference: add lda
|
2014-11-29 11:04:13 +08:00 |
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8f18d8d492
|
devices: use underscore in filenames to permit import
|
2014-11-29 11:03:52 +08:00 |
|
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8593ac85fd
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doc/manual/writing_a_driver: use underscore in filenames
|
2014-11-29 10:57:23 +08:00 |
|
Yann Sionneau
|
81ab801fe4
|
lda: filter reports when waiting for command response
|
2014-11-29 10:50:41 +08:00 |
|
Yann Sionneau
|
075e540032
|
lda: separate simulation class
|
2014-11-29 10:50:12 +08:00 |
|
Yann Sionneau
|
b9e7fdb80e
|
lda: add docstring
|
2014-11-29 10:49:43 +08:00 |
|
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44ec3eae3d
|
soc/target: use minicon by default
|
2014-11-28 10:21:43 +08:00 |
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41ecf09873
|
doc/manual/installing: add missing cd
|
2014-11-27 22:27:18 +08:00 |
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6e219469fe
|
py2llvm: support operations between fractions and floats
|
2014-11-27 18:52:45 +08:00 |
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f12389cdd4
|
doc/manual: add controller default TCP port list
|
2014-11-25 20:24:57 +08:00 |
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dc27c2e3ad
|
lda: remove excessive verbosity
|
2014-11-25 19:59:53 +08:00 |
|
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|
57e25c7af1
|
lda: minor fixes and refactoring
|
2014-11-25 19:56:28 +08:00 |
|
Yann Sionneau
|
744e7841c6
|
devices: initial LDA controller
|
2014-11-25 19:51:28 +08:00 |
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|
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a3f981726a
|
units: error checking
|
2014-11-22 16:56:51 -08:00 |
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d59d110f78
|
doc/manual: add ports to index
|
2014-11-21 18:08:40 -08:00 |
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ab88c6d0b8
|
transforms/lower_units: fix bugs and add unit test
|
2014-11-21 18:08:14 -08:00 |
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8d59f843fb
|
doc/manual: add FPGA board info and TTL line assignments
|
2014-11-21 16:39:22 -08:00 |
|
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|
35d4f75b65
|
transforms: PEP8
|
2014-11-21 15:55:39 -08:00 |
|
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|
65567e1201
|
soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY
|
2014-11-21 15:51:51 -08:00 |
|
|
|
1f92e19f2b
|
transforms/fold_constants: support decimal fractions
|
2014-11-21 15:51:20 -08:00 |
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|
57cc6479c4
|
pyon: fraction support
|
2014-11-21 11:30:37 -08:00 |
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