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1423 Commits

Author SHA1 Message Date
Robert Jördens 593dafc118 test: hardware testbench 2015-06-28 20:55:59 -06:00
Robert Jördens 39e9e73ff3 language: allow experiments to import from artiq.language 
this way the import stanza shows what is imported: just experiment language
related components

keep the imports also at top level until experiments have transitioned

the top level __init__.py should build and expose the entire namespace of artiq
related things, like hdf5 analysis tools, frontend components (like experiment
running api), deployment tools etc.
 2015-06-28 20:52:41 -06:00
whitequark f430bf3f63 Add support for exceptions. 2015-06-29 00:35:48 +03:00
whitequark a4a9cd884e Add exception constructor types. 2015-06-28 22:48:15 +03:00
whitequark 9044e88983 Elaborate hierarchy of builtins. 2015-06-28 22:40:57 +03:00
Sebastien Bourdeauducq 944bfafefa soc: support QC2 and AD9914 (untested) 2015-06-28 21:37:27 +02:00
Sebastien Bourdeauducq b6310b72db runtime: fix log formatting 2015-06-28 17:29:52 +02:00
Sebastien Bourdeauducq 85c5b157a0 test/full_stack: tolerate FP rounding errors 2015-06-27 23:52:20 +02:00
Sebastien Bourdeauducq 8b5b219a18 runtime: provide fixdfdi 2015-06-27 23:51:48 +02:00
Sebastien Bourdeauducq 3bd7f11737 update lwip 2015-06-27 22:48:41 +02:00
Sebastien Bourdeauducq 2d475e146b runtime/flash_storage: use log not printf 2015-06-27 22:47:36 +02:00
Sebastien Bourdeauducq 7d3acf4d10 Merge branch 'master' of https://github.com/m-labs/artiq 2015-06-27 21:15:24 +02:00
Sebastien Bourdeauducq a7bbcdc1ad targets/pipistrello: mon -> moninj 2015-06-27 21:15:17 +02:00
Robert Jördens 07ceed9512 artiq_flash.sh: back down on verbosity 2015-06-26 11:09:26 -06:00
Yann Sionneau c381102019 manual: fix faq item title about determining pyserial URL by serial number 2015-06-26 18:22:47 +02:00
whitequark ea0d11b8be Allow also passing iterables to lists. 2015-06-26 19:14:24 +03:00
whitequark e07057c224 Add range types. 2015-06-26 18:53:20 +03:00
whitequark 71256a7109 Assignment rhs is typed before lhs. 2015-06-26 18:35:34 +03:00
Sebastien Bourdeauducq c71fe29792 simplify unit system and use floats by default 2015-06-26 16:34:37 +02:00
Sebastien Bourdeauducq e6a4c2fb36 dds: make it easier to specify phase 2015-06-26 12:05:11 +02:00
whitequark 7cd6011981 Add typechecking for most builtin. 2015-06-26 11:16:08 +03:00
Robert Jördens dd2c1d1b72 travis: try again with latest conda 2015-06-25 13:50:38 -06:00
Robert Jördens 48e0a2ad37 artiq_flash: echo commands for a bit more verbosity 2015-06-25 13:28:05 -06:00
Robert Jördens 52030ab1b7 travis: export MACADDR, do not source get-xilinx 2015-06-25 13:08:56 -06:00
Robert Jördens b820b7a3e1 Revert "travis: use latest miniconda" 
Seems to segfault on travis.

This reverts commit 51eb835030.
 2015-06-25 12:56:50 -06:00
Robert Jördens 51eb835030 travis: use latest miniconda 2015-06-25 12:50:09 -06:00
Robert Jördens 1c7ab97b91 travis: cleanup unused/redundant env vars 2015-06-25 12:40:04 -06:00
Robert Jördens 31d551e619 travis: cleanup get-xilinx.sh a bit 2015-06-25 12:35:50 -06:00
Yann Sionneau 9c96ebf7d4 nist_qc2: add fmc adapter io file 2015-06-25 03:06:15 +02:00
whitequark 752031147d Add valid forms for builtin calls. 2015-06-24 12:16:17 +03:00
whitequark 4d407ace4b Implement prelude. 2015-06-24 11:46:15 +03:00
whitequark 710a04cbee Add builtin definitions for len(), round(), range() and syscall(). 2015-06-24 11:28:24 +03:00
whitequark 8762729e80 Add types.TBuiltin. 2015-06-24 11:24:35 +03:00
Sebastien Bourdeauducq 064ddb48bd manual: minor fixes 2015-06-23 19:44:02 +00:00
Sebastien Bourdeauducq 4ba8951ae1 rpc: fix indentation of class docstring 2015-06-23 19:31:52 +00:00
Yann Sionneau 71721a152e artiq_rpctool: list-methods also prints class docstring 2015-06-23 18:35:32 +02:00
Yann Sionneau f0dddd9f39 manual: hwgrep is the preferred way of specifying a serial device 2015-06-23 18:14:25 +02:00
Yann Sionneau 7821d0f7c8 manual: explain how to list attached serial devices on windows/linux 2015-06-23 17:05:57 +02:00
Robert Jördens 5b3eac1d96 pipistrello: tweak fifo depths a bit 
ise being dull again, inferring all but one 64x64 fifo as bram...
minimum bram depth is 256 anyway
 2015-06-22 23:25:07 -06:00
Robert Jördens cd249b2f66 pipistrello: run at 83+1/3 MHz, cleanup CRG 2015-06-22 19:03:00 -06:00
Sebastien Bourdeauducq 9f3f9255a2 soc: increase DDS output FIFO sizes 2015-06-21 08:40:10 -06:00
Sebastien Bourdeauducq b7d976e7db ddb: fix pdq comment 2015-06-21 08:39:58 -06:00
Sebastien Bourdeauducq 8082bf14c1 Merge branch 'master' of https://github.com/m-labs/artiq 2015-06-21 07:27:47 -06:00
Robert Jördens ef96de7d26 Merge branch 'shrink-dds-wb' 
* shrink-dds-wb:
  ad9858: make wb data 8 bit wide
 2015-06-21 00:10:44 -06:00
Robert Jördens 45ec5dbe84 ad9858: make wb data 8 bit wide 
matches actual dds bus data width and saves bram
 2015-06-20 23:53:01 -06:00
Robert Jördens 07a58dc0da wavesynth: cleanup, refactor 2015-06-20 23:29:26 -06:00
Robert Jördens e94e7c6a75 examples/ddb: make rtio_frame a list (json compat) 2015-06-20 23:29:26 -06:00
Sebastien Bourdeauducq 87ea1433d3 dds: all working 2015-06-20 18:42:39 -06:00
Sebastien Bourdeauducq c8fba45db5 Merge branch 'master' of https://github.com/m-labs/artiq 2015-06-19 21:59:44 -06:00
Sebastien Bourdeauducq 827f99e7d3 gui: more digits in DDS monitor 2015-06-19 17:55:01 -06:00