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c3953d85d5
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master/client: periodic schedule support
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2014-12-10 19:11:13 +08:00 |
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347410afa2
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master/client: queue display and cancellations
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2014-12-10 13:04:18 +08:00 |
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0dc4eb02ae
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setup: install frontend tools, remove nosetest dependency, minor fixes
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2014-12-10 12:13:10 +08:00 |
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87fdad97ca
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devices/lda: break off main function
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2014-12-10 12:01:31 +08:00 |
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eb42cf2bb4
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doc/manual/installing: LLVM_CONFIG_PATH does not work with the llvmlite ffi makefile. Use PATH instead.
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2014-12-10 10:52:38 +08:00 |
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46e78a4ff1
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doc/manual/installing: fix paths (thanks Joe)
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2014-12-10 10:46:03 +08:00 |
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08f2aa8503
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management/scheduler: replace queue with transparent list + semaphore
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2014-12-09 16:26:50 +08:00 |
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059608d1fd
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dds: fix phase modes
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2014-12-09 13:50:33 +08:00 |
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9628e1d013
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manual/installing: remove useless cd
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2014-12-09 11:28:38 +08:00 |
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cb48dba29c
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coredevice: fix external clock ref_period computation
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2014-12-09 11:22:55 +08:00 |
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597fe57fb3
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pyon: unit support
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2014-12-09 10:48:47 +08:00 |
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e814da1ba3
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master/client: use dpdb and file import
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2014-12-08 19:22:02 +08:00 |
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123656e2cd
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fractions: fix comparison
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2014-12-08 19:21:16 +08:00 |
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72c24ba320
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identify_controller -> artiq_ctlid
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2014-12-08 16:12:39 +08:00 |
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fd28bfbb7c
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artiq_run: reference module by filename
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2014-12-08 16:11:31 +08:00 |
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bfe980d458
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py2llvm: distinguish between llvmlite Module and ModuleRef
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2014-12-06 15:14:39 +08:00 |
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b830dd527c
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test/py2llvm: pep8
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2014-12-06 14:54:41 +08:00 |
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9165031fd5
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test/py2llvm: support 32-bit machines
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2014-12-06 14:52:33 +08:00 |
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0e9c9b25b0
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README: update
|
2014-12-05 17:14:52 +08:00 |
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159f632a65
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switch to llvmlite
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2014-12-05 17:05:43 +08:00 |
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b93b969e2a
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doc/pc_rpc: add warning about mutable types
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2014-12-04 18:04:54 +08:00 |
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044756287f
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test: add serialization
|
2014-12-04 17:52:22 +08:00 |
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4c7749bd01
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pyon: partial JSON compatibility
|
2014-12-03 23:46:59 +08:00 |
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fd8f3be946
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pyon: pretty printing
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2014-12-03 23:25:51 +08:00 |
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2a95d27770
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device and parameter database
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2014-12-03 18:20:30 +08:00 |
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a41009f92a
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coredevice/comm_dummy: support clock-switching functions
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2014-12-03 18:16:18 +08:00 |
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5b8f34bae2
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language/core/kernel: support return values
|
2014-12-03 17:21:26 +08:00 |
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85b4d70ced
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pyon: add file I/O functions
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2014-12-03 17:18:43 +08:00 |
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6de650a701
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doc/manual: minor fixes
|
2014-12-02 19:23:15 +08:00 |
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2a843ea436
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language: replace AutoContext 'parameter' string with abstract attributes
This allows specifying default values for parameters, and other data.
|
2014-12-02 17:19:05 +08:00 |
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83d3b97b23
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coredevice/comm_serial: give up on garbage received after baudrate change
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2014-12-02 16:04:41 +08:00 |
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cad5933709
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transforms/inline: do not writeback bool
|
2014-12-02 15:53:41 +08:00 |
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649fedd656
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coredevice/core: fix recover_underflow
|
2014-12-02 15:31:09 +08:00 |
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fc690ead75
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runtime: support clock switching
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2014-12-02 14:06:32 +08:00 |
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94218f785e
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comm_serial: cleanup
|
2014-12-02 11:09:02 +08:00 |
|
Yann Sionneau
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20adb57140
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comm_serial: allow to use dynamic baudrate
|
2014-12-02 10:42:14 +08:00 |
|
Yann Sionneau
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3ff3afe696
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manual: use theme options which looks like m-labs web site
|
2014-12-02 10:32:27 +08:00 |
|
Yann Sionneau
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0c20445413
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lda: allow to simulate without needing hidapi
This also fixes some old style string formating
|
2014-12-01 19:39:13 +08:00 |
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c591f1a74d
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targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
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2014-12-01 18:53:29 +08:00 |
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57d633f48e
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rtio: remove unnecessary attributes
|
2014-12-01 17:47:24 +08:00 |
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cd587e4f12
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rtio: do housekeeping in gateware
|
2014-12-01 17:32:36 +08:00 |
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99d530e498
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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
|
2014-12-01 17:31:35 +08:00 |
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3a27f49bff
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frontend/runelf: use new Comm
|
2014-12-01 15:24:38 +08:00 |
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2146e58d20
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frontend: rename files to avoid conflicts
|
2014-12-01 15:20:35 +08:00 |
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50e0bf3280
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rtio: optimize flag handling
|
2014-12-01 14:29:50 +08:00 |
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572eecc57b
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rtio: stricter upper bound on guard time to avoid race condition
|
2014-12-01 14:27:03 +08:00 |
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d50dbc0e73
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coredevice/runtime_exceptions: update RTIO exception behaviour doc
|
2014-12-01 13:57:25 +08:00 |
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7166ca82d1
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targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
|
2014-11-30 22:31:55 +08:00 |
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1f6441948d
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more TTL channels and larger input FIFOs on Papilio Pro
|
2014-11-30 15:50:57 +08:00 |
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e5286c57ab
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rtio: fix input FIFO depth config
|
2014-11-30 12:12:35 +08:00 |
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