Florent Kermarrec
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1f0d955ce4
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drtio/transceiver/gtp: implement tx multi lane phase alignment sequence
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2018-02-27 12:32:25 +01:00 |
Sebastien Bourdeauducq
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f060d6e1b3
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drtio: increase A7 clock aligner check period
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2018-02-20 18:50:35 +08:00 |
Florent Kermarrec
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89a158c0c9
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drtio/transceiver/gtp_7series_init: remove dead code
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2018-02-19 10:02:23 +01:00 |
Sebastien Bourdeauducq
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83abdd283a
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drtio: signal stable clock input to transceiver
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2018-02-18 22:29:30 +08:00 |
Florent Kermarrec
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bfdda340fd
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drtio/transceiver/gtp_7series: use parameters from xilinx wizard
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2018-02-13 00:23:59 +01:00 |
Florent Kermarrec
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180c28551d
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drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
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2018-02-09 20:17:02 +01:00 |
Sebastien Bourdeauducq
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d6157514c7
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gtp_7series: flexible QPLL channel selection
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2018-01-23 12:03:09 +08:00 |
Sebastien Bourdeauducq
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98a5607634
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gtp_7series: set clock muxes correctly for second QPLL channel
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2018-01-23 10:39:20 +08:00 |
Sebastien Bourdeauducq
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25fee1a0bb
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gtp_7series: use QPLL second channel
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2018-01-23 10:15:49 +08:00 |
Sebastien Bourdeauducq
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626075cbc1
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gtp_7series: simplify TX clocking
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2018-01-23 09:49:23 +08:00 |
Sebastien Bourdeauducq
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401e57d41c
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gtp_7series: fix nchannels assert
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2018-01-23 01:28:01 +08:00 |
Sebastien Bourdeauducq
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5198c224a2
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sayma,kasli: use new pin names
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2018-01-22 11:51:07 +08:00 |
Florent Kermarrec
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d27727968c
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add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
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2018-01-19 12:17:54 +01:00 |