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7978 Commits

Author SHA1 Message Date
occheung 798774192d slave_fpga/bootloader: read in little endian 2021-09-10 13:25:12 +08:00
occheung eecd825d23 firmware: suppress warning 2021-09-10 13:25:12 +08:00
occheung 1da0554a49 pcr: purge 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 035d15af9d flake: clean up vivado, add installer environment 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9addd08587 flake: fetch MiSoC submodules 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 3e09e48152 flake: set up Vivado 2021-09-10 13:25:12 +08:00
occheung 5d0a8cf9ac llvm_ir_gen: fix indent 2021-09-10 13:25:12 +08:00
occheung 70507e1b72 Cargo.lock: update 2021-09-10 13:25:12 +08:00
occheung c113cd6bf5 libfringe: bump 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 251cd4dcc6 flake: update dependencies 2021-09-10 13:25:12 +08:00
occheung 61b0170a12 firmware: purge or1k 2021-09-10 13:25:12 +08:00
occheung af263ffe1f ksupport: fix rpc, cache signature (FFI) 
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
 2021-09-10 13:25:12 +08:00
occheung a833974b50 analyzer: fix endianness 2021-09-10 13:25:12 +08:00
occheung d623acc29d llvm_ir_gen: fix now with now_pinning & little-endian target 2021-09-10 13:25:12 +08:00
occheung 8fa47b8119 rpc: enforce alignment 2021-09-10 13:25:12 +08:00
occheung de0f2d4a28 firmware: adopt endianness protocol in artiq-zynq 
Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
 2021-09-10 13:25:12 +08:00
occheung 9afe63c08a ksupport: fix proto_artiq dependency 2021-09-10 13:25:12 +08:00
occheung 29a2f106d1 ksupport: replace asm with llvm_asm 2021-09-10 13:25:12 +08:00
occheung b30ed75e69 kernel.ld: load elf header and prog headers 
ld.lld has a habit of not putting the headers under any load sections.
However, the headers are needed by libunwind to handle exception raised by the kernel.
Creating PT_LOAD section with FILEHDR and PHDRS solves this issue. Other PHDRS are also specified as linkers (not limited to ld.lld) will not create additional unspecified headers even when necessary.
 2021-09-10 13:25:12 +08:00
occheung 279593f984 ksupport.ld: merge sbss with bss 2021-09-10 13:25:12 +08:00
occheung 1ba8c8dfee runtime: remove irq again 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 942bd1a95d flake: add hydraJobs 2021-09-10 13:25:12 +08:00
occheung 3d629006df makefiles: revert byte-swaps 2021-09-10 13:25:12 +08:00
occheung 7542105f0f board_misoc: remove pcr 
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
 2021-09-10 13:25:12 +08:00
occheung 01ca114c66 runtime: remove irq dependency 2021-09-10 13:25:12 +08:00
occheung 36171f2c61 runtime: remove inaccurate sp on panic 2021-09-10 13:25:12 +08:00
occheung 01e357e5d3 ksupport.ld: reduce load section alignment 2021-09-10 13:25:12 +08:00
occheung f77b607b56 compiler: generate symbols 2021-09-10 13:25:12 +08:00
occheung 1293e0750e ld, makefiles: use ld.lld 2021-09-10 13:25:12 +08:00
occheung fc42d053d9 kernel: use vexriscv 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9adab6c817 flake: add devshell 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 8c468d0346 flake: switch to nightly rust with mozilla overlay 2021-09-10 13:25:12 +08:00
occheung 1b516b16e2 targets: default to vexriscv cpu 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq be5ae5c5b4 flake: configure binary cache 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq d13efd6587 add Nix flake 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq e8fe8409b2 libartiq_support: compatibility with recent stable rustc 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq cabe5ace8e compiler: remove DebugInfoEmitter for now 
Causes problems with LLVM 9 and not needed at first.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 6629a49e86 compiler: use LLVM binutils/linker for Arm as well 
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 43d120359d compiler: switch to upstream llvmlite and RISC-V target 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 5656e52581 remove profiler 2021-09-10 13:25:12 +08:00
occheung 1b8b4baf6a ksupport: fix panic, libc, unwind 2021-09-10 13:25:12 +08:00
occheung 905330b0f1 ksupport: handle riscv exceptions 2021-09-10 13:25:12 +08:00
occheung 50a62b3d42 liballoc: change align to 16 bytes 2021-09-10 13:25:12 +08:00
occheung 7f0bc9f7f0 runtime/makefile: specify emulation, flip endianness 2021-09-10 13:25:12 +08:00
occheung c42adfe6fd runtime.ld: merge .sbss & .bss 2021-09-10 13:25:12 +08:00
occheung f56152e72f rust: fix dependencies 2021-09-10 13:25:12 +08:00
occheung c800b6c8d3 runtime: update rust alloc, managed 2021-09-10 13:25:09 +08:00
occheung e99061b013 runtime: add riscv 2021-09-10 13:23:22 +08:00
occheung ecedec577c runtime: impl riscv exception handling 2021-09-10 13:23:15 +08:00
occheung 252594a606 runtime: impl riscv panic handler 2021-09-10 13:20:31 +08:00