2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 21:26:37 +08:00
Commit Graph

15 Commits

Author SHA1 Message Date
Florent Kermarrec
f003566e52 serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
2017-11-18 18:01:46 +01:00
Florent Kermarrec
1b976bfa4d gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x 2017-11-18 17:57:11 +01:00
Florent Kermarrec
48bfaec8d3 gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8 2017-11-10 10:37:08 +01:00
Florent Kermarrec
59be095512 gateware/serwb/kusphy: use locally inverted clk_b on iserdese3 2017-11-10 10:35:48 +01:00
Florent Kermarrec
db82b11f29 gateware/serwb/core: cleanup and increase fifo depth 2017-11-10 10:33:39 +01:00
Florent Kermarrec
5bd1e43ced gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
Florent Kermarrec
660f9856ec gateware/serwb: add test for phy initialization 2017-08-30 17:59:10 +02:00
Florent Kermarrec
9650233007 gateware/serwb: change serdes clock domain to serwb_serdes 2017-08-30 15:44:44 +02:00
Florent Kermarrec
41d57d64f6 gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
Florent Kermarrec
7d7f6be7ce gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction 2017-08-29 16:41:29 +02:00
Florent Kermarrec
60ad36e7d6 gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready 2017-08-29 13:43:26 +02:00
Florent Kermarrec
89558e2653 gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
2017-08-29 13:38:52 +02:00
53c7f92fdc serwb: add __init__.py and expose submodules 2017-08-21 15:57:43 -04:00
dac3a78b75 serwb: style, use migen, fix imports 2017-08-21 12:35:59 -04:00
Florent Kermarrec
44dc76e42e Add serial Wishbone bridge
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
2017-08-21 12:22:05 -04:00