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artiq
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1164 Commits

Author SHA1 Message Date
whitequark 0e7294db8d Null-terminate all string literals. 2015-07-21 19:57:18 +03:00
whitequark 9d20080624 Use internal linkage for interior Python global values. 2015-07-21 19:55:43 +03:00
whitequark 8c9d9cb5a1 Make compiler.testbench.llvmgen emit a main() function. 2015-07-21 19:48:44 +03:00
whitequark 7301a76d68 Mark string constants as unnamed_addr. 
As a result they will be merged when possible.
 2015-07-21 17:10:31 +03:00
whitequark 49ece6a12a Add support for string literals. 2015-07-21 14:27:48 +03:00
whitequark 64d2604aa8 Tolerate assertion failures in tests when looking for diagnostics. 2015-07-21 14:12:27 +03:00
whitequark e58b811d6d Fix tests broken by fixed FloorDiv. 2015-07-21 14:05:07 +03:00
whitequark ec9d40b04f Add LLVM IR generation for function calls. 2015-07-21 13:45:27 +03:00
whitequark e299801c0f LocalAccessValidator: fix validation of closures with no outer variables. 2015-07-21 13:16:18 +03:00
whitequark 6f11fa6bb1 Add conversion to LLVM IR (except handling of exception handling). 2015-07-21 04:55:01 +03:00
whitequark c6cd318f19 Fix artiq.compiler.ir.BasicBlock.__repr__. 2015-07-19 16:32:33 +03:00
whitequark 7e3f91c0bb Teach closures to LocalAccessValidator. 2015-07-19 12:08:26 +03:00
whitequark 2c010b10ee Remove UnaryOp ARTIQ IR instruction; rename BinaryOp to Arith. 
Everything it can express can also be expressed via Arith.
 2015-07-19 11:51:53 +03:00
whitequark ac491fae47 Add LocalAccessValidator. 2015-07-19 11:44:51 +03:00
whitequark f5d9e11b38 Remove irgen tests. 
These are too hard to write and will be replaced by integration
tests of ARTIQ IR generator + LLVM IR generator once the latter
gets implemented.
 2015-07-19 11:30:53 +03:00
whitequark adf18bb042 Fix assignment to tuples in IRGenerator. 2015-07-19 10:31:11 +03:00
whitequark 4bd83fb43d Use ".k" instead of "k" for the finalizer continuation variable. 
The dot signifies that this is an internal variable and it
does not need to be tracked as if it was a user-defined one.
 2015-07-19 10:30:42 +03:00
whitequark 8eedb3bc44 Fix IRGenerator.append(loc=...). 2015-07-19 10:29:33 +03:00
whitequark f212ec0263 Add a trivial dead code elimination transform. 
Its purpose is to sweep up basic blocks with no predecessors,
which are annoying to handle explicitly elsewhere.
 2015-07-19 10:29:14 +03:00
whitequark 603d49dffa Add a dominator analysis. 2015-07-18 20:48:52 +03:00
whitequark 224a93fde3 Make compiler.ir.BasicBlock.predecessors much faster. 2015-07-18 20:48:11 +03:00
whitequark 47cbadb564 Revert "Ensure bindings are created in correct order for e.g. "x, y = y, x"." 
This reverts commit bcd1832203.

The bindings are actually created in lexical order, as evident
in e.g. "x = lambda: x". The safety provided by this check should
be instead provided by a local access analysis.
 2015-07-18 09:54:11 +03:00
whitequark 8e1cc8d985 Add an explicit ARTIQ IR instruction to create a closure. 2015-07-18 09:27:34 +03:00
whitequark 5ad02d5282 Fix ARTIQ IR generation for variables declared global. 2015-07-18 09:10:41 +03:00
whitequark 21eafefd28 Fix inference for globals. 2015-07-18 08:13:49 +03:00
whitequark 0d66bdfbf8 Fix For miscompilation. 2015-07-18 07:58:43 +03:00
whitequark dde2e67c3f Add source locations to ARTIQ IR instructions. 2015-07-18 07:49:42 +03:00
whitequark 255ffec483 Generate more compact ARTIQ IR for else-less if. 2015-07-18 07:49:27 +03:00
whitequark e96bc3c36c Add complete IR generator. 2015-07-17 21:29:06 +03:00
whitequark f28549a11a Add builtins.is_exception. 2015-07-17 16:05:02 +03:00
whitequark 3b661b2b65 Fix environment corruption by ExceptHandler without a name. 2015-07-17 16:04:46 +03:00
whitequark 2dcb744519 Fix inference for default arguments. 2015-07-16 17:26:31 +03:00
whitequark f8e51e07d5 Add zero/one accessors to TBool, TInt, TFloat. 2015-07-16 16:03:24 +03:00
whitequark bcd1832203 Ensure bindings are created in correct order for e.g. "x, y = y, x". 2015-07-16 15:59:59 +03:00
whitequark 5756cfcebc Correctly infer type of list(iterable). 2015-07-16 15:35:46 +03:00
whitequark 6cda67c0c6 Ensure type comparisons see through type variables. 2015-07-16 14:59:05 +03:00
whitequark c1e7a82e97 Add IndexError and ValueError builtins. 2015-07-16 14:58:40 +03:00
whitequark b58fa9067d Add attributes to TRange. 
Also make attributes an OrderedDict, for stable order during
LLVM IR generation.
 2015-07-16 14:57:44 +03:00
whitequark a6950bf11d Move builtin.is_{builtin,exn_constructor} to types. 2015-07-16 14:56:39 +03:00
whitequark 5000f87dfc Rename the field of CoerceT from expr to value. 2015-07-16 14:55:23 +03:00
whitequark e9416f4707 Convert Slice into typed SliceT. 2015-07-16 14:54:04 +03:00
whitequark 53fb03d1bf Restrict comprehensions to single for and no if clauses. 2015-07-16 14:52:41 +03:00
whitequark 227f97f8a3 Add inference for Index, Slice and ExtSlice. 2015-07-16 04:22:41 +03:00
whitequark c724e024ce Fix inference for multiple-target assignments. 2015-07-15 06:33:44 +03:00
whitequark 9ff9f85f19 Add accessors to instructions. 2015-07-14 22:18:38 +03:00
whitequark bdcb24108b Add basic IR generator. 2015-07-14 08:56:51 +03:00
whitequark f417ef31a4 Make binop coercion look through CoerceT nodes. 
This fixes inference for "x = 1 + 1" after int monomorphization.
 2015-07-14 06:42:09 +03:00
whitequark ebe243f8d9 Add printing of SSA functions. 2015-07-13 21:08:20 +03:00
whitequark dbdd45acc5 Add missing return. 2015-07-13 20:52:55 +03:00
whitequark 7c9afcce85 Fix Python default argument fiasco. 2015-07-13 20:52:48 +03:00