M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

Remove irgen tests. 

These are too hard to write and will be replaced by integration
tests of ARTIQ IR generator + LLVM IR generator once the latter
gets implemented.
This commit is contained in:
whitequark 2015-07-19 11:30:53 +03:00
parent adf18bb042
commit f5d9e11b38
4 changed files with 0 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lit-test/compiler/irgen/empty.py
View File

@ -1,7 +0,0 @@
# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
# RUN: OutputCheck %s --file-to-check=%t
# CHECK-L: NoneType input.__modinit__() {
# CHECK-L: 1:
# CHECK-L: return NoneType None
# CHECK-L: }

9
lit-test/compiler/irgen/eval.py
View File

@ -1,9 +0,0 @@
# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
# RUN: OutputCheck %s --file-to-check=%t
2 + 2
# CHECK-L: NoneType input.__modinit__() {
# CHECK-L: 1:
# CHECK-L: %2 = int(width=32) eval `2 + 2`
# CHECK-L: return NoneType None
# CHECK-L: }

21
lit-test/compiler/irgen/if.py
View File

@ -1,21 +0,0 @@
# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
# RUN: OutputCheck %s --file-to-check=%t
if 1:
2
else:
3
# CHECK-L: NoneType input.__modinit__() {
# CHECK-L: 1:
# CHECK-L: %2 = int(width=32) eval `1`
# CHECK-L: branch_if int(width=32) %2, ssa.basic_block %3, ssa.basic_block %5
# CHECK-L: 3:
# CHECK-L: %4 = int(width=32) eval `2`
# CHECK-L: branch ssa.basic_block %7
# CHECK-L: 5:
# CHECK-L: %6 = int(width=32) eval `3`
# CHECK-L: branch ssa.basic_block %7
# CHECK-L: 7:
# CHECK-L: return NoneType None
# CHECK-L: }

25
lit-test/compiler/irgen/while.py
View File

@ -1,25 +0,0 @@
# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
# RUN: OutputCheck %s --file-to-check=%t
while 1:
2
else:
3
4
# CHECK-L: NoneType input.__modinit__() {
# CHECK-L: 1:
# CHECK-L: branch ssa.basic_block %2
# CHECK-L: 2:
# CHECK-L: %9 = int(width=32) eval `1`
# CHECK-L: branch_if int(width=32) %9, ssa.basic_block %5, ssa.basic_block %7
# CHECK-L: 4:
# CHECK-L: branch ssa.basic_block %7
# CHECK-L: 5:
# CHECK-L: %6 = int(width=32) eval `2`
# CHECK-L: branch ssa.basic_block %7
# CHECK-L: 7:
# CHECK-L: %8 = int(width=32) eval `3`
# CHECK-L: %13 = int(width=32) eval `4`
# CHECK-L: return NoneType None
# CHECK-L: }