M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

jesd204: use jesd clock domain for sysref sampler 

RTIO domain is still in reset during calibration.
This commit is contained in:
Sebastien Bourdeauducq 2018-06-22 17:12:59 +08:00
parent 76fc63bbf7
commit f87da95e57
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/jesd204_tools.py
View File

@ -108,5 +108,5 @@ class SysrefSampler(Module, AutoCSR):
self.sample_result = CSRStatus() self.sample_result = CSRStatus()
sample = Signal() sample = Signal()
self.sync.rtio += If(coarse_ts[:4] == 0, sample.eq(jref)) self.sync.jesd += If(coarse_ts[:4] == 0, sample.eq(jref))
self.specials += MultiReg(sample, self.sample_result.status) self.specials += MultiReg(sample, self.sample_result.status)