From f87da95e57d253ff5b6f46c1fc636aaca2d30898 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 22 Jun 2018 17:12:59 +0800 Subject: [PATCH] jesd204: use jesd clock domain for sysref sampler RTIO domain is still in reset during calibration. --- artiq/gateware/jesd204_tools.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 0e35b055e..8187e4999 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -108,5 +108,5 @@ class SysrefSampler(Module, AutoCSR): self.sample_result = CSRStatus() sample = Signal() - self.sync.rtio += If(coarse_ts[:4] == 0, sample.eq(jref)) + self.sync.jesd += If(coarse_ts[:4] == 0, sample.eq(jref)) self.specials += MultiReg(sample, self.sample_result.status)