mirror of https://github.com/m-labs/artiq.git
sawg: special case Config RTIO address
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@ -15,7 +15,17 @@ class Channel(_ChannelPHY):
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def __init__(self, *args, **kwargs):
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_ChannelPHY.__init__(self, *args, **kwargs)
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self.phys = []
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for i in self.i:
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cfg = self.i[0]
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rl = rtlink.Interface(rtlink.OInterface(
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data_width=len(cfg.data), address_width=len(cfg.addr)))
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self.comb += [
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cfg.stb.eq(rl.o.stb),
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rl.o.busy.eq(~cfg.ack),
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cfg.data.eq(rl.o.data),
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cfg.addr.eq(rl.o.address),
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]
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self.phys.append(_Phy(rl, [], []))
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for i in self.i[1:]:
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload),
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delay=-i.latency))
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self.comb += [
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@ -89,6 +89,8 @@ class SAWGTest(unittest.TestCase):
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if isinstance(data, list):
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data = sum(int(d) << (i*32) for i, d in enumerate(data))
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yield rt.data.eq(int(data))
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if hasattr(rt, "address"):
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yield rt.address.eq(address)
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yield rt.stb.eq(1)
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assert not (yield rt.busy)
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# print("{}: set ch {} to {}".format(time, channel, hex(data)))
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