From f4c6879c76e257ed994eab4b511bd83edbb97d73 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 21 Jun 2017 14:28:36 +0200 Subject: [PATCH] sawg: special case Config RTIO address --- artiq/gateware/rtio/phy/sawg.py | 12 +++++++++++- artiq/gateware/test/dsp/test_sawg_fe.py | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/rtio/phy/sawg.py b/artiq/gateware/rtio/phy/sawg.py index 9bbce3c04..093a235c4 100644 --- a/artiq/gateware/rtio/phy/sawg.py +++ b/artiq/gateware/rtio/phy/sawg.py @@ -15,7 +15,17 @@ class Channel(_ChannelPHY): def __init__(self, *args, **kwargs): _ChannelPHY.__init__(self, *args, **kwargs) self.phys = [] - for i in self.i: + cfg = self.i[0] + rl = rtlink.Interface(rtlink.OInterface( + data_width=len(cfg.data), address_width=len(cfg.addr))) + self.comb += [ + cfg.stb.eq(rl.o.stb), + rl.o.busy.eq(~cfg.ack), + cfg.data.eq(rl.o.data), + cfg.addr.eq(rl.o.address), + ] + self.phys.append(_Phy(rl, [], [])) + for i in self.i[1:]: rl = rtlink.Interface(rtlink.OInterface(len(i.payload), delay=-i.latency)) self.comb += [ diff --git a/artiq/gateware/test/dsp/test_sawg_fe.py b/artiq/gateware/test/dsp/test_sawg_fe.py index caac32a5c..0a55f12d7 100644 --- a/artiq/gateware/test/dsp/test_sawg_fe.py +++ b/artiq/gateware/test/dsp/test_sawg_fe.py @@ -89,6 +89,8 @@ class SAWGTest(unittest.TestCase): if isinstance(data, list): data = sum(int(d) << (i*32) for i, d in enumerate(data)) yield rt.data.eq(int(data)) + if hasattr(rt, "address"): + yield rt.address.eq(address) yield rt.stb.eq(1) assert not (yield rt.busy) # print("{}: set ch {} to {}".format(time, channel, hex(data)))