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sawg: special case Config RTIO address

This commit is contained in:
Robert Jördens 2017-06-21 14:28:36 +02:00
parent ff0da2c9fc
commit f4c6879c76
2 changed files with 13 additions and 1 deletions
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12
artiq/gateware/rtio/phy/sawg.py
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@ -15,7 +15,17 @@ class Channel(_ChannelPHY):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):
_ChannelPHY.__init__(self, *args, **kwargs) _ChannelPHY.__init__(self, *args, **kwargs)
self.phys = [] self.phys = []
for i in self.i: cfg = self.i[0]
rl = rtlink.Interface(rtlink.OInterface(
data_width=len(cfg.data), address_width=len(cfg.addr)))
self.comb += [
cfg.stb.eq(rl.o.stb),
rl.o.busy.eq(~cfg.ack),
cfg.data.eq(rl.o.data),
cfg.addr.eq(rl.o.address),
]
self.phys.append(_Phy(rl, [], []))
for i in self.i[1:]:
rl = rtlink.Interface(rtlink.OInterface(len(i.payload), rl = rtlink.Interface(rtlink.OInterface(len(i.payload),
delay=-i.latency)) delay=-i.latency))
self.comb += [ self.comb += [

2
artiq/gateware/test/dsp/test_sawg_fe.py
View File

@ -89,6 +89,8 @@ class SAWGTest(unittest.TestCase):
if isinstance(data, list): if isinstance(data, list):
data = sum(int(d) << (i*32) for i, d in enumerate(data)) data = sum(int(d) << (i*32) for i, d in enumerate(data))
yield rt.data.eq(int(data)) yield rt.data.eq(int(data))
if hasattr(rt, "address"):
yield rt.address.eq(address)
yield rt.stb.eq(1) yield rt.stb.eq(1)
assert not (yield rt.busy) assert not (yield rt.busy)
# print("{}: set ch {} to {}".format(time, channel, hex(data))) # print("{}: set ch {} to {}".format(time, channel, hex(data)))